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Intel Architecture
Software Developer’sManual
Volume 3:System Programming
NOTE
: The
 Intel Architecture Software Developer’s Manual
consists of three volumes:
 Basic Architecture
, Order Number 243190;
Instruction Set  Reference,
Order Number 243191; and the
System Programming Guide,
Order Number 243192.Please refer to all three volumes when evaluating your design needs.
1999
 
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppelor otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms andConditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or impliedwarranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particularpurpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products arenot intended for use in medical, life saving, or life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts orincompatibilities arising from future changes to them.Intel’s Intel Architecture processors (e.g., Pentium®, Pentium® II, Pentium® III, and Pentium® Pro processors) maycontain design defects or errors known as errata which may cause the product to deviate from publishedspecifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing yourproduct order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature,may be obtained by calling 1-800-548-4725, or by visiting Intel's literature center at http://www.intel.com.
COPYRIGHT © INTEL CORPORATION 1999*THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS.
 
iii
TABLE OF CONTENTS
CHAPTER 1ABOUT THIS MANUAL
1.1.P6 FAMILY PROCESSOR TERMINOLOGY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2.OVERVIEW OF THE
INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL,VOLUME 3 
: SYSTEM PROGRAMMING GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.3.OVERVIEW OF THE
INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL,VOLUME 1
: BASIC ARCHITECTURE 1-31.4.OVERVIEW OF THE
INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL,VOLUME 2 
: INSTRUCTION SET REFERENCE 1-51.5.NOTATIONAL CONVENTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.5.1.Bit and Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-61.5.2.Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-61.5.3.Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.5.4.Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.5.5.Segmented Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-71.5.6.Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-81.6.RELATED LITERATURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
CHAPTER 2SYSTEM ARCHITECTURE OVERVIEW
2.1.OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE . . . . . . . . . . . . . . . . . . . 2-12.1.1.Global and Local Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32.1.2.System Segments, Segment Descriptors, and Gates. . . . . . . . . . . . . . . . . . . . . .2-32.1.3.Task-State Segments and Task Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42.1.4.Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42.1.5.Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52.1.6.System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52.1.7.Other System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62.2.MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62.3.SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER . . . . . . . . . . . . . . . . 2-82.4.MEMORY-MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.4.1.Global Descriptor Table Register (GDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-102.4.2.Local Descriptor Table Register (LDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112.4.3.IDTR Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112.4.4.Task Register (TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112.5.CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122.5.1.CPUID Qualification of Control Register Flags . . . . . . . . . . . . . . . . . . . . . . . . . .2-182.6.SYSTEM INSTRUCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-182.6.1.Loading and Storing System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-202.6.2.Verifying of Access Privileges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-202.6.3.Loading and Storing Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-212.6.4.Invalidating Caches and TLBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-212.6.5.Controlling the Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-222.6.6.Reading Performance-Monitoring and Time-Stamp Counters . . . . . . . . . . . . . .2-222.6.7.Reading and Writing Model-Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . .2-232.6.8.Loading and Storing the Streaming SIMD Extensions Control/Status Word. . . .2-23
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