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Interrupts Microchip PIC With CCS-C

Interrupts Microchip PIC With CCS-C

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Published by: ascensorim on Jul 17, 2012
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08/21/2015

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2012
MSEE Ibrahim GULESINAdministrator16/07/2012
MICROCHIPPICANDCCS-CINTERRUPTS
 
Ing.Ibrahim GULESIN
TakingTimingFurther
Brief information about interrupts, timer/counter operation, PWM pulse width modulation andCCS Pic-C applications on these topics.
PIC16 F84A interrupts and TIMERO module
PIC16 F877A interrupts and TIMERO, TIMER1, TIMER2 modules
PIC16 F877A Capture/Compare/Pulse-width-modulation CCP module
Interrupts
Interrupts and timing are two most important topics in studying microcontrollers. Correct andefficient use of related hardware PIC MCU sources and software capabilities will ease manyadvanced engineering studies. CCS Pic-C compiler provides various high-level language featuresthat may be utilized in related studies. Bearing in mind that, lecture notes, datasheet, compilerhelp and examples should be consulted for their proper use, the following information will serveas a guide to these studies.
16F84AInterruptStructure
16 F84A has four maskable interrupt sourcesExternal interrupt source:This is the only external interrupt input. It is edge triggered.Associated pin: RBO/INTTimer overflow interrupt:Caused by the Timer O module. It occurs when the timer's 8-bit counter overflowsPort B interrupt on change:This interrupt occurs when any of the higher 4 bits of Port B(RB7:RB4) changes.EEPROM write complete:Occurs when a write instruction to EEPROM memory iscompleted.
 
Ing.Ibrahim GULESIN
16F84AInterruptLogicStructure
Interrupt logic structure of 16F84A is shown below. The 5 FR that controls it is the INTCON registerand OPTION register. INTCON register contains enable bits of all interrupt sources and OPTIONregister contain interrupt edge select bit of external interrupt sourceEach source has an enable line (labeled by E) and a flag line (labeled by F, actually these are theinterrupt flags, rather than interrupt sources).
Note:All four 16 F84A interrupts can be enabled or disabled (maskable). Interrupt flag bits are setwhen an interrupt condition occurs, regardless of the state of its corresponding enable bit orthe global enable bit.

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