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Table Of Contents

2.4SYNTHESIS
3.1.2Comments
3.1.3Numbers
3.1.4Verilog Data Type
Example 3.1Verilog Code Using Wire Declaration
Example 3.3Verilog Code Using Reg Declaration
Example 3.4Verilog Code Using Reg Declaration for an 8-bit Bus
Example 3.5Verilog Code Showing a Tri Declaration
3.1.5Signal Strength
Example 3.6Verilog Code Using Strength Assignment
3.2VERILOG GATE-LEVEL PRIMITIVES
TABLE 3.9.Table showing different strength levels
TABLE 3.10.Truth table for pmostransistor primitive
TABLE 3.11.Truth table for nmostransistor primitive
TABLE 3.12.Truth table for cmospassgate primitive
TABLE 3.13.Truth table for notif0 tri-state inverter primitive
TABLE 3.14.Truth table for notif1 tri-state inverter primitive
TABLE 3.15.Truth table for bufif0 tri-state buffer primitive
TABLE 3.16.Truth table for bufif1 tri-state buffer primitive
3.3USER-DEFINED PRIMITIVES
3.3.1Combinational UDP
Example 3.7Example Showing Syntax Defining a UDP
3.3.2Sequential UDP
TABLE 3.20.Concurrent and sequential statements
3.4CONCURRENT AND SEQUENTIAL STATEMENTS
Coding Style: Best-Known Method for Synthesis
4.1NAMING CONVENTION
4.2DESIGN PARTITIONING
4.3CLOCK
4.3.1Internally Generated Clock
Example 4.2Verilog Code for the Design of Figure 4.4
4.3.2Gated Clock
FIGURE 4.5.Diagram showing a gated clock driving a flip-flop
4.4RESET
4.4.1Asynchronous Reset
Example 4.6Verilog Code for an Asynchronous Reset Design
4.4.2Synchronous Reset
Example 4.7Verilog Code for a Synchronous Reset Design
4.5TIMING LOOP
FIGURE 4.10.Diagram showing a design with timing loop
4.7SENSITIVITY LIST
Complete Sensitivity List Incomplete Sensitivity List
4.8VERILOG OPERATORS
4.8.1Conditional Operators
Example 4.17Verilog Code for Module “conditional”
4.8.2Bus Concatenation Operator
4.8.3Shift Operator
Example 4.19Verilog Code Using the Shift Left Operator
Example 4.22Verilog Code Using the Shift Right Operator
“shift_right_tb.”
4.8.4Arithmetic Operator
Example 4.25Verilog Code Using an Addition Operator
Example 4.28Verilog Code Using a Subtraction Operator
Example 4.31Verilog Code Using a Multiplication Operator
4.8.5Division Operator
Example 4.34Verilog Code Using a Division Operator
4.8.6Modulus Operator
Example 4.37Verilog Code Using a Modulus Operator
4.8.7Logical Operator
Example 4.40Verilog Code Using Logical Operators
4.8.8Bitwise Operator
Example 4.43Verilog Code Using Bitwise Operators
4.8.11Relational Operator
Example 4.52Verilog Code Using Relational Operators
4.9LATCH INFERENCE
Example 4.56Verilog Code for Incomplete “case” Statement
4.10MEMORY ARRAY
Example 4.60Verilog Code for a 1-kilobyte Memory Array
4.11STATE MACHINE DESIGN
4.11.1Intelligent Traffic Control System
FIGURE 4.36.Diagram showing an interchange junction traffic light
CONTROLLER
TABLE 4.3.Interface Signal Description for Traffic Light Controller
state_machine
Design Example of Programmable Timer
5.1PROGRAMMABLE TIMER DESIGN SPECIFICATION
FIGURE 5.1.Diagram showing bits of control word register
5.2MICROARCHITECTURE DEFINITION FOR PROGRAMMABLE TIMER
TABLE 5.1.Signal description for programmable timer design
5.3FLOW DIAGRAM DEFINITION FOR PROGRAMMABLE TIMER
FIGURE 5.5.Flow diagram for reset of programmable timer
FIGURE 5.6.Flow diagram for mode 0 operation
FIGURE 5.7.Flow diagram for mode 1 operation
FIGURE 5.8.Flow diagram for mode 2 operation
5.4VERILOG CODE FOR PROGRAMMABLE TIMER
Example 5.1Verilog Code for Programmable Timer
5.5SYNTHESIZABLE VERILOG CODE FOR PROGRAMMABLE TIMER
FIGURE 6.1.Diagram showing interface signals of PLB
TABLE 6.1.Table showing a description of PLB’s interface signals
6.2.1Mode 0 Operation
6.2.2Mode 1 Operation
6.2.3Mode 2 Operation
FIGURE 6.22.Diagram showing generation of set_so_intralogic
FIGURE 6.23.Diagram showing generation of set_si_intralogic
FIGURE 6.24.Diagram showing generation of intralogic
FIGURE 6.25.Diagram showing generation of set_so_intrblogic
FIGURE 6.26.Diagram showing generation of set_si_intrblogic
FIGURE 6.27.Diagram showing generation of intrblogic
FIGURE 6.31.Diagram showing multiplexing of signals to portA
FIGURE 6.32.Diagram showing multiplexing of signals to portB
FIGURE 6.33.Diagram showing multiplexing of signals to portC
Example 6.1Synthesizable Verilog Code for PLB
6.6SIMULATION FOR PROGRAMMABLE PERIPHERAL INTERFACE DESIGN
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Wiley.verilog.coding.for.Logic.synthesis.ebook Spy

Wiley.verilog.coding.for.Logic.synthesis.ebook Spy

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Published by: Krishna Chaitanya Makkena on Jul 27, 2012
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