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Verilog Basics 8 FSM

Verilog Basics 8 FSM

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Published by Ahmad Shdifat
Digital System Design - Verilog by Dr. Bassam Jamil Hashemite University
Digital System Design - Verilog by Dr. Bassam Jamil Hashemite University

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Published by: Ahmad Shdifat on Jul 29, 2012
Copyright:Attribution Non-commercial

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05/13/2014

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Digital System Design Verilog: Finite State Machine
Dr. Bassam Jamil
 
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Finite State Machine (FSM) Definition
FSM is a behavioral model which is used torepresent an software/hardware algorithm.
FSM consists of states, transitions
State: FSM consists of finite number of states, whereeach state represent unique configuration of thesystem.
Transition is an action initiated by a condition. It startsfrom one state and ends in another/same state.
 
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FSM Definition: More of Digital DesignDefinition

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