Nilanjan Mukherjee Prof. Sudhakar Reddy C. P.

Ravikumar

Presenters
2

Presenters: 1.

Nilanjan Mukherjee Mentor Graphics Corporation

nilanjan_mukherjee@mentor.com

2.

Prof. Sudhakar Reddy University of Iowa

reddy@engineering.uiowa.edu

3.

C. P. Ravikumar Texas Instruments, India ravikumar@ti.com

Outline - Day 1
3

Introduction CAD Tools

Coffee Break

(9:00 am 10:00 am) (10:00 am 10:45 am) (11:00 am 12:30 pm) (2:00 pm 2:30 pm) (2:30 pm 4:00 pm) (4:15 pm 5:00 pm)

Logic Test Basics

Lunch

Logic Test Advanced Fault Models

Coffee Break

Advanced Fault Models

Outline - Day 2
4

Power Aware Test DFT

Coffee Break

(9:00 am 10:00 am) (10:00 am 10:45 am) (11:00 am 11:15 am) (11:15 am 12:30 pm)

DFT Logic BIST

Lunch

Logic BIST Memory Test Memory Test

(2:00 pm 2:45 pm) (2:45 pm 4:00 pm)

Coffee Break

(4:15 pm 5:00 pm)

Outline - Day 3
5

Test Compression
Coffee Break

(9:00 am 10:30 am) (11:00 am 12:30 pm)

Fault Diagnosis
Lunch

Industrial Experiences

(2:00 pm 4:30 pm)

Acknowledgements
6

Xioagang Du, Mentor Graphics Dhiraj Goswami, Mentor Graphics Ruifeng Guo, Intel Xijiang Lin, Mentor Graphics Srinivas Patil, Intel Janusz Rajski, Mentor Graphics Nagesh Tamarapalli, Mentor Graphics Nandu Tendolkar, Freescale Jerzy Tyszer, Poznan Institute of Technology

Acknowledgements
7

Sudhakar Reddy acknowledges the help of University of Iowa graduate students Zhuo Zhang, Santiago Remersaro, Chen Liu, Narendra Devtaprasanna

Outline - Day 1
8

Introduction CAD Tools

Coffee Break

(9:00 am 10:00 am) (10:00 am 10:45 am) (11:15 am 12:30 pm) (2:00 pm 2:45 pm) (2:45 pm 4:00 pm) (4:30 pm 5:30 pm)

Logic Test Basics

Lunch

Logic Test Advanced Fault Models

Coffee Break

Advanced Fault Models

Outline
10

Design Characteristics Defects on DSM Circuits Systematic vs. Random Defects Objectives of Digital Testing Defect Coverage, Yield, Test Quality Functional vs. Structural Tests Benefits of Structural Tests Factors Affecting Test

Nanometer Designs Test Challenges

11

180 nm 90 nm

Growing gate counts

Exploding test data volume Unacceptable test application times

Complex SoC architectures

Multiple test methods required Embedded memory everywhere

Small geometries + new materials = new defect types

Resistive bridging & vias Traditional stuck-at testing is not enough
Resistive via

R
R = 50 K Delay of 250ps How do you test for it?

Growing Complexity - ITRS

12

Year Node [nm] Devices [million tr.] Voltage [V] Oxide thickness [nm] Static power per dev

2001 130 276 1.2 2.3 1.00

2004 90 553 1.0 2.0 1.96

2007 65 1106 0.7 1.4 9.46

2010 45 2212 0.6 1.2 17.32

2013 32 4424 0.5 1.0 25.00

2016 22 8848 0.4 0.9 19.64

Intel transistor technology evolution

G. Spirakis, Intel, ETW02

70nm

System-on-a-Chip Characteristics
13

System architecture
Microprocessors, DSP cores Buses, peripherals, memory ASIC portion
CPU core

DSP core IP core

ASIC

Memory

ASIC

Memory

Structures: Logic, memory, analog Multiple embedded memories: SRAM, DRAM, Flash, CAM Analog and mixed signal: PLLs, clock recovery Field programmable logic RF cores: wireless receivers IP cores and reusable blocks available from multiple vendors Design efficiency achieved by hierarchical core-based design style

I/0
IP core

Memory Memory Memory

ASIC Analog ASIC

PLL

Complex Interconnects Many Features

14

100 million gates 400 million transistors Billions of vias 6 km of wire / cm2

90 nm interconnects, Intel Nigh, IBM, ITC01

Process Shrinks vs. Defect Types

15

Defect Pareto 350 nm

Unknown BridgeM1-2 Via break Bridge M2 Bridge M4 Break trans Bridge Poly M2 Bridge M3 Bridge M1-3 Bridge poly M1 Bridge M3-4 Open Poly Open Contact Bridge M1 Unknown Br Break M3 Bridge Poly M2 Break M2 Bridge M3-4 Break M1 Bridge Poly M4 Bridge Poly

350 nm Process 5 million Transistors

Al 4-5 Levels

W Plugs Oxide Dielectric

A Transistor

Process Shrinks vs. Defect Types

16

Defect Pareto 100 nm 100 nm Process -- 250 million transistors

Unknown

?
Defect distribution change with process

Cu (8 Levels)

Low-K Dielectric

Cu Plugs

A Transistor

New Defect Types

17

Resistive shorts

Vias

Gelsinger, Intel, ITC 99

Nigh, IBM, ITC01

Many additional small delays

Quality Requirements
18

Escapes

1-p

nt me hip s

Faults detected

1-Y

Quality Requirements
19 Escapes = (1 - Y)(1 - p)

0.01 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0
0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000

Yield = 0.9

Yield = 0.1

What is Yield?
20

Fabrication Electrical Test Fab Metrology Wafer Sort Assembly Final Test

Historical Initial Yield1

21

25% 20% 15% 10% 5% 0% 500 250 180 130 90 65 nm

1M.

Rencher and G. Allan,GDSII Yield Signoff Methods, Design for Yield, EE Times

Design Re-spins
22
100 90 80 70 Rate (%) 60 50 40 30 20 10 0 350 250 180 Technology Node (nm)
Source: Mark Miller, eeDesign.com, 2004

First Time Design Success Full Reticle Set Respins

130

90

The Systematic Yield Crisis

23

Target

130nm 350nm 250nm 90nm

Types of Defects in Nanometer Designs

24

Manufacturing Test Requirements

25

Feature related defects are becoming more prevalent than particle-driven defects in nanometer designs1 Better and more effective (Higher Quality) testing is necessary to maintain quality (or DPM) levels

1 Hsu and Chen TSMC: Scan Diagnostics in the Nanometer Design Era; Semiconductor Manufacturing, March 2006.

Yield, DPM, and Test Quality

26

DPM is a function of yield and test quality As yield decreases, DPM increases Highest test quality is needed just to maintain DPM levels

Why not Functional Tests?

27

Functional tests are tests developed to mimic functional behavior of the circuit Disadvantages

Requires detailed circuit knowledge Expensive development and troubleshooting Difficult to create high coverage patterns Complicated failure diagnosis Often requires high performance testers Large inter-dependent test sets

Why Structural Tests?

28

Targeted for detecting manufacturing defects in the device Use fault models to enable test generation

Correlates to defects Proven in industry Predictable results Provides high coverage tests, quickly

Can be automated and is repeatable

What is DFT?
29

Inserts structures inside the IC to make it easier to test Generates test sets Provides measures of test quality Diagnoses the cause of a failing device

Improves Product Quality

30

Test quality impacts your product quality Assume 90% yield and 1M chips shipped/yr

99% defect coverage => 1053 defective chips are shipped 95% defect coverage => 5254 defective chips are shipped Includes coverage for all defects: at-speed, bridging, stuck-open, etc.

Defect coverage is not just stuck-at coverage

Shortens Time-to-Market
31

Time-to-market pressures

More test (e.g. at-speed) Higher coverage Bigger designs Longer runtimes

DFT tools must keep pace with design technologies and test methodologies

Increased integration Increased automation Improved performance

Reduces Test Cost

32

DFT reduces test set sizes

Reduces ATE memory requirements Reduces test time Minimizes or eliminates tester reloads Improves tester throughput

Tester Capacity Limit

Coverage
Test Cost

Escapes
Pattern Volume

Traditional Fault Models

33

Stuck-at-0 and stuck-at-1 Transitions Path delay Iddq

VDD

IDDQ Testing
34

Models high current flow through a gate Measures quiescent power supply current during the stable state Involves measuring current - not logic values
VDD
A B 0 0/1 Y P1 1/ 0 0

A B

P2

Y
1/0

0 N2 N1 Faulty transistor stuck on

VSS

IDDQ Testing
35

Iddq
1000

PolySi PolySi
PolySi

100

10
Silicon

Silicon

1 130 90 65 45 32 22

G. Spirakis Intel, ETW02

Technology nodes

Effectiveness of Iddq test is fading Scan test needs to compensate

Quality is Driving Change

36

At 130 nanometer and below, stuck-at test alone is not sufficient

Fabless Forum March 2003

Mentor Graphics & Nvidia - Fabless Forum, March 2003

At-Speed Test Effect on DPM

LSI* experiments

37

ASIC 1 2 3 4 5

Technology 0.18m 0.18m 0.18m 0.18m 0.18m

At .18m 1% defects were speed-related At .13m 2% defects were speed-related 30-70% DPM reduction w/at-speed test

DPM reduction 70% 59% 60% 33% 33%

Intel** claims 1-5% of defects are at-speed failures

* Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs VTS 2003. ** Delay Defect Characteristics and Testing Strategies IEEE Design & Test of Computers, Sept-Oct 2003.

Phases of Test
38

Fabrication Fabrication

Wafer Test Wafer Test

Slice & Dice, Package Slice & Dice, Package Burn-in, Burn-in, Packaged Part Test Packaged Part Test Ship to Customer Ship to Customer

Our focus is here

Test Program Components

39

Test programs can contain various test sets

DC Parametric Test logic verification DC logic stuck-at AC frequency assessment AC logic delay Memory testing Memory retention IDDQ test Specialty vectors

Factors Affecting Test

40

ATE characteristics define DFT constraints Examples

Scan configuration Test pattern generation Test coverage Test application time Cost of test Diagnosis

Conclusions
41

Better and more effective testing is necessary to maintain quality (or DPM) levels

Scan test and diagnostics are playing an increasingly important role in failure analysis and yield learning