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DIGITAL ELECTRONICS LABORATORY MANUAL

Department of Electronics and Communication Engineering


National Institute of Technology, Tiruchirappalli 620 015 Lab In charges: Mr.P.Palanisamy Mr.G.Thavasi Raja

CONTENTS
1. STUDY OF LOGIC GATES AND VERIFICATION OF BOOLEAN LAWS 2. DESIGN OF ADDERS AND SUBTRACTORS 3. DESIGN AND IMPLEMENT CODE CONVERTERS 4. DESIGN OF MULTIPLEXER 5. DESIGN OF DEMULTIPLEXER 6. DESIGN OF ENCODER AND DECODER 7. 2 BIT AND 8-BIT MAGNITUDE COMPARATOR 8. STUDY OF FLIP FLOPS 9. DESIGN AND IMPLEMENTATION OF COUNTERS USING FLIP FLOPS 10. DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS 11. APPENDIX Clock Generators Introduction to ORCAD/PSPICE

EX NO: 1 DATE:

STUDY OF LOGIC GATES AND VERIFICATION OF BOOLEAN LAWS

AIM: 1. To study of Logic gates. 2. To verify Boolean laws APPARATUS REQUIRED: S.No. 1 2 3 4 5 6 7 8 9 10 11 APPARATUS Power supply Bread Board Resistor LED Quad-2-input NAND Quad-2-input NOR Quad-2-input AND Quad-2-input OR Quad-2-input XOR Hexa inverter gate Connecting wires Specification / Range 0-5 V 330 7400 7402 7408 7432 7486 7404 Qty 1 1 1 1 1 1 1 1 1

THEORY: Basic gates like AND, OR, NOR, EXOR etc. form the building blocks of complicate ICs. They are generally available as quadrature ICs. NOR and NAND gates are called the universal gates, as any other gate can be form may be realized using these. GATES AND THEIR CHARACTERISTICS AND: output is high when both the inputs are high OR: output is high if any input is high NOT: output is invert of input NAND: output is high when one or both the inputs are high. NOR: output is high when both inputs are low XOR: output is high when one of the inputs is high XNOR: output is high when both inputs are identical. PROCEDURE: 1. Test all the ICs using IC tester. 2. Place the IC in the breadboard. 3. Connect Vcc and the ground. 4. Connect the appropriate pins to the input and out LEDs and switches. 5. Give various combinations of the inputs and observe the output and verify the truth table 6. Repeat the above steps for all the ICs.

AND
14 13 12 11 10 9 8

Vcc
1 3 2 2 1 3

7408

1 3 2

1 3 2

GND 1 2 3 4 5 6

SYMBOL A
1 3 2

Y=A.B

B
TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUTPUT 0 0 0 1

OR
14 13 12 11 10 9 8

Vcc
1 3 2 2 1 3

7432
1 3 2 2 1 3

GND 1 2 3 4 5 6

SYMBOL A
1 2

Y=A+B
3

B
TRUTH TABLE:

A 0 0 1 1

B 0 1 0 1

OUTPUT 0 1 1 1

NAND
14 13 12 11 10 9 8

Vcc
1 3 2 2 1 3

7400
1 3 2 2 1 3

GND
1 2 3 4 5 6 7

SYMBOL A
1 3 2

Y= (A.B) '

B
TRUTH TABLE

A 0 0 1 1

B 0 1 0 1

OUTPUT 1 1 1 0

EXOR
14 13 12 11 10 9 8

Vcc
2 1 3 3 2 1

7486
2 1 3 3 2 1

GND
1 2 3 4 5 6 7

SYMBOL A
2 1 3

Y=A +

B
TRUTH TABLE

A 0 0 1 1

B 0 1 0 1

OUTPUT 0 1 1 0

EXNOR
14 13 12 11 10 9 8

Vcc
2 1 3 3 2 1

74286

2 1 3

2 1 3

GND
1 2 3 4 5 6 7

SYMBOL A B
TRUTH TABLE

2 1 3

Y=A

A 0 0 1 1

B 0 1 0 1

OUTPUT 1 0 0 1

NOT
14 13 12 11 10 9 8

Vcc
1 2 1 2 1 2

7404

.
1

GND
1 2 3 4 5 6 7

SYMBOL A
1

Y= A
2

A 0 1

OUTPUT 1 0

NOR
14 13 12 11 10 9 8

Vcc
3 1 2 1 2 3

7402
3 1 2 1 2 3

GND
1 2 3 4 5 6 7

SYMBOL A
2 3

B
TRUTH TABLE

A 0 0 1 1

B 0 1 0 1

OUTPUT 0 Y= 0A+B 0 0

Verification of Boolean Laws Boolean algebra is a systematic arrangement of logic which analyses the logic and arithmetic calculation of all digital equipments. Boolean algebra operates with logic expressions containing Logic variables Logic operators Parenthesis Equal sign

Commutative Law For AND operation For OR operation AB=BA A+B=B+A

This can be proved from the respective truth tables

Associative Law For AND operation For OR operation A (BC) = (AB) C A+ (B+C) = (A+B) +C

E.g. 1*(1*0) = (1*1)*0 = 0 1+ (1+0) = (1+1) +0 = 1

Distributive Law For AND operation For OR operation A*(B+C) = AB + AC A+ (B*C) = (A+B) *(A+C)

E.g. 1*(1+0) = (1*1) + (1*0) = 1 1+ (1*0) = (1+1) * (1+0) = 1

Identity Law For AND operation A+A = A

For OR operation A*A = A The AND and OR operation obey Identity Law. If both the inputs are same, output is same. E.g. 1+1 = 1 1*1 = 1

Complement Law For AND operation For OR operation _ A*A = 0 _ A+A = 1

The complement law is obeyed in different ways by AND and OR gates. In case of OR, the output is always 1, and in AND, it is always 0.

Operation with 0 & 1 For AND operation For OR operation A*0 = 0 A*1 = A A+0 = A A+1 = 1

AND with 0 yields 0 as output. AND with 1 yields input as output. OR with 0 yields input as output. OR with 1 yields 1 as output.

De-Morgans Laws The complement of sum of 2 Boolean variables is equal to the product of the individual complements _____ _ _ A+B=A*B The complement of product of 2 Boolean variables is equal to the sum of the individual complements _____ _ _ A*B=A+B Double Complement _ _ A=A Double complement of an input yields the same output. Redundancy Laws A + AB = A A + AB = A [1+B] = A [1] =A

_ A + AB = A + B _ A + AB = A + B _ = A + AB + AB _ = A + B [A + A] = A + B*1 = A +B A (A+B) = A A (A+B) = A*A + A*B = A + AB = A [1+B] = A*1 =A _ A (A+B) = AB _ _ A (A+B) = A*A + A*B = 0 + A*B = AB

A+B=B+A A B
1 2

A+B
3

B A

1 2

B+A
3

TRUTH TABLE A 0 0 1 1 B 0 1 0 1 A+B 0 1 1 1 B+A 0 1 1 1

A.B=B.A A B
1 2 3

A.B

B A

1 2

B.A

TRUTH TABLE A 0 0 1 1 B 0 1 0 1 AB 0 0 0 1 BA 0 0 0 1 A A+1 0 1 1 1

A+1=1 A 5V 1
3 2

TRUTH TABLE

A.1=A A 5V
1 3 2

TRUTH TABLE A A.1 0 0 1 1

A+0=A A
1 3 2

TRUTH TABLE A A+0 0 0 1 1

A.0=0 A1
3 2

TRUTH TABLE A A.0 0 0 1 0

A+A=A
1

3 2

TRUTH TABLE A A+A 0 0 1 1

A.A=A
1

3 2

TRUTH TABLE A A.A 0 0 1 1

A + A=1

2 1

1
3

TRUTH TABLE A A 0 1 1 0 A+A 1 1

A . A=0
1 2 1 3 2

TRUTH TABLE A A A.A 0 1 0 1 0 0

RESULT:

Exp no : 2 Date: AIM:

DESIGN OF ADDERS AND SUBTRACTORS

1. To design and test a half and full adder 2. To design and test a half and full subtractor. APPARATUS REQUIRED: S.NO 1. 2. 3. 3. THEORY: HALF ADDER: Half adders are capable of taking two inputs only. Their outputs are sum and carry. Adders are circuits which are used to find the sum of the inputs. FULL ADDER: These adders are capable of having three inputs and they produce two outputs: sum and carry. Since three inputs are present, eight input combinations are possible whereas in half adder only four input combinations are possible. APPARATUS Bread board ICs 7486,7408,7432 Power supply Patch Chords QUANTITY 1 1 each 1

HALF ADDER: SYMBOL:

X Y
TRUTH TABLE: X 0 0 1 1 From the truth table, S= XY C= XY

HALF ADDER

SUM(S) CARRY(C)

Y 0 1 0 1

S 0 1 1 0

C 0 0 0 1

CIRCUIT DIAGRAM:

X Y

2 1 3 IC 7486

1 3 2 IC 7408

FULL ADDER: SYMBOL:

A B C
TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1

SUM(S) FULL ADDER CARRY(C)

Cout 0 0 0 1 0 1 1 1

SIMPLIFICATION: Sum S = A B C Carry C = AB+BC+CA

CIRCUIT DIAGRAM:
IC 7486 2 1 3 3 2 1 IC 7486

SUM(S)

IC 7408A 1 3 2 1 3 IC 7408A 1 3 2 1 3 2 IC 7408A 1 3 2 IC 7432A 2 IC 7432A

CARRY(C)

Theory: Subtractors are circuits used to find the difference between the inputs. Half Subtractor: These have 2 inputs( 4 input combinations possible ) and 2 outputs. Difference and Borrow. Full Subtractor: These have 3 inputs ( 8 input combination possible ) and 2 outputs. Difference and Borrow. Procedure: 1. 2. 3. 4. 5. Test all the ICs using the IC tester. Place the ICs in the slots in breadboard and lock it in place. Connect Vcc and ground. Connect the appropriate inputs to the switches and outputs to the LEDs. Give various combinations of inputs and verify the truth table.

HALF SUBTRACTOR: INPUTS X 0 0 1 1 From truth table: Y 0 1 0 1 OUTPUTS B 0 1 0 0 D 0 1 1 0

_ B = XY _ _ D = XY + XY = X Y

CIRCUIT DIAGARM FOR HALF SUBTRACTOR:

FULL SUBTRACTOR:
TRUTH TABLE: INPUTS X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 OUTPUTS B 0 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1 D

SIMPLIFICATION: YZ 00 X 0 1 0 0 01 1 0 1 1 11 1 0 10

_ _ B= XZ + YZ + XY _ _ = YZ + X (Y+Z) X YZ 00 0 1 1 1 1 01 11 1 10

D = X YZ

FULL SUBTRACTOR:

RESULT:

Ex No:3 AIM: To implement

DESIGN AND IMPLEMENT CODE CONVERTERS

(i) Binary to gray code converter (ii) Gray to binary code converter Equipments required Sno 1 2 3 3 Theory The gray code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers. The boolean expressions are G3=D G2=C (+) D G1=B (+) C G0=A (+) B The binary code is a 2 bit code. It is a weighted code with the digits in each position having a weight of 2.It is used in computers. A=(G3 (+) G2) (+) (G1 (+) G0) B=G3 (+) G2 (+) G1 C=G3 (+) G2 D=G3 Procedure 1.Place the IC's on a bread board. 2.Connect circuit as per logic diagram. 3.Apply input and verify output. Component Bread board EX-OR gate Power supply Connecting wires Range IC7486 (0-5)V Quantity 1 2 1 as required

Truth Table: BINARY D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 GRAY G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

K-Map Simplification: G0 0 1 0 1 0 1 0 1 G0=A (+) B G1 0 0 1 1 1 1 0 0 G1=B (+) C G2 0 0 1 1 0 0 1 1 G2=C (+) D G3 0 0 0 0 1 1 1 1 G3=D

0 0 0 0

1 1 1 1

1 0 0 1

1 0 0 1

0 1 0 1

0 1 0 1

0 0 1 1

0 0 1 1

Circuit Diagram: Binary to Gray Code Converter:

Truth Table GRAY G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BINARY B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

K-Map Simplification: A 0 1 0 1 0 1 0 1 0 1 0 1 A=(G3(+)G2) (+) (G1 (+)G0 ) B 0 0 1 1 1 0 0 0 1 1 1 0 B= G3 (+) G2 (+) G1 C 0 0 0 1 1 1 0 0 0 1 1 1 C=G3 (+) G2 D 0 0 0 0 0 0 1 1 1 1 1 1 D=G3 Circuit Diagram: Gray to Binary Code Converter:

1 0 1 0

1 0 1 0

0 1 0 1

0 0 1 1

Result:

EX NO:4 DATE: AIM:

DESIGN OF MULTIPLEXER

To design and implement a 4:1 mux APPARATUS REQUIRED: S.NO APPARATUS 1. Breadboard 2. ICs 7411(3-i/p AND), 7404,7432 3 Power supply .4 Patch Chords THEORY: MULTIPLIXERS: It has 2n inputs and 1 output controlled by n control lines whose status selects which of the 2n inputs will occur as output. It is used as a data selector. DESIGN OF MUX : 2:1 MUX SYMBOL:
2 : 1 MUX

QUANTITY 1 1 each 1

OUTPUT

2 INPUTS

SELECT LINE

Y = s I o + s I1 S 0 0 1 1 I0 0 1 X x I1 X X 0 1 Y 0 1 0 1
Ic7408
1 2 1 3 1 3 2 2

Ic7432

I0

Ic7404

4
5

I1

4:1 MUX SYMBOL:

D0 D1 D2 D3 4 : 1 MUX Y

S1

S0

TRUTH TABLE: INPUTS A1 A2 0 0 1 0 0 1 0 0 SELECT LINES S1 S0 0 0 0 1 1 0 1 1 OUTPUT Y A0S1S0 A1S1S0 A2S1S0 A3S1S0

A0 1 0 0 0

A3 0 0 0 1

CIRCUIT DIAGRAM:

A0

1 2 8

1 3 2 2 2 1 3 1 3

A1

1 2 8

A2

1 2 8

A3

1 2 8

S0

S1

Procedure 1.Place the IC's on a bread board. 2.Connect circuit as per logic diagram. 3.Apply input and verify output.

PIN Diagram for IC 74153 (Dual MUX) and IC7411 (3 i/p AND):

4:1 MUX Using IC 74153:


__ __ __ __

Go = 0

G1 = 1 1Y A0 B0 C0 D0 S0 0 0 1 1

Go = 1 G1 = 0

S0 0 0 1 1

S1 0 1 0 1

S1 0 1 0 1

2Y A1 B1 C1 D1

8:1 MUX using IC74153:

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

O/P A0 B0 C0 D0 A1 B1 C1 D1

FULL Adder Using IC74153:

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Sum 0 0 0 1 0 1 1 1

Carry 0 1 1 0 1 0 0 1

RESULT:

EX NO: 5 DATE: AIM:

DESIGN OF DEMULTIPLEXER

To design and implement a 1: 4 demux APPARATUS REQUIRED: S.NO 1. 2. 3. 3. THEORY: DEMULTIPLEXER: It performs the reverse action of that of a multiplexer. A single input is demultiplexed by n select lines to give 2n outputs. Procedure: 1.Place the IC's on a bread board. 2.Connect circuit as per logic diagram. 3.Apply input and verify output. DEMULTIPLEXER: SYMBOL:
INPUT 1 : 2n DEMUX 2 OUTPUTS

APPARATUS Bread board ICs 7411,7404,7432 Power supply Patch Chords

QUANTITY 1 1 each 1

1:2 DEMUX TRUTH TABLE D 0 0 1 1 S 0 1 0 1 Y0 0 0 1 0 Y1 0 0 0 1

n SELECT LINES

1: 2 DEMUX Circuit Diagram:

1:4 DEMUX SYMBOL:

Y0 D 1 : 4 DEMUX Y1 Y2 Y3

1:4 DEMUX TRUTH TABLE: S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 Y0 0 1 0 0 0 0 0 0 Y1 0 0 0 1 0 0 0 0 Y2 0 0 0 0 0 1 0 0 Y3 0 0 0 0 0 0 0 1

1:4 DEMUX Circuit Diagram:


A
1 2

B
1 2 1 2 8

Y0

1 2 8

Y1

1 2 8

Y2

PIN Diagram of IC74155:


D
1 2 8 9

Y3

1:4 DEMUX Circuit Diagram: Input Output S1 X X 0 1 0 1 Y0 1 1 0 1 1 1 Y1 1 1 1 0 1 1 Y2 1 1 1 1 0 1 Y3 1 1 1 1 1 0


__

Da
X 1 0 0 0 0

Ga
1 X 0 0 0 0

S0 X X 0 0 1 1

Input

Output S1 X X 0 1 0 1 Y4 1 1 0 1 1 1 Y5 1 1 1 0 1 1 Y6 1 1 1 1 0 1 Y7 1 1 1 1 1 0

Db
X 1 1 1 1 1

__

Gb
1 X 0 0 0 0

S0 X X 0 0 1 1

1:8 DEMUX Circuit Diagram:

__

G0
X 0 0 0 0 0 0 0 0

S2 X 0 0 0 0 1 1 1 1

S1 X 0 0 1 1 0 0 1 1

S0 X 0 1 0 1 0 1 0 1

Y0 1 0 1 1 1 1 1 1 1

Y1 1 1 0 1 1 1 1 1 1

Y2 1 1 1 0 1 1 1 1 1

Y3 1 1 1 1 0 1 1 1 1

Y4 1 1 1 1 1 0 1 1 1

Y5 1 1 1 1 1 1 0 1 1

Y6 1 1 1 1 1 1 1 0 1

Y7 1 1 1 1 1 1 1 1 0

RESULT:

EX NO:6 DATE: Aim:

DESIGN OF ENCODER AND DECODER

1. To design encoder and verify their truth table. 2. To design decoder and verify its truth table. Equipments Required: Sl.No. 01. 02. 03. 04. Theory: Encoder: An encoder in a digital function that produces a reverse operation from that of a n decoder. An encoder has 2 input lines and n output lines. Decoder: A decoder is a combinational circuit that converts binary information from n inputs to a n maximum of 2 unique output. If the n bit decoded information has the decoder output n will have less than 2 outputs. The decoder presented here are called line decoders where m n m s 2 their purpose generate the 2 minterms of n input variables. The name decoder is also used in conjunction with some code converter such as a BCD to seven segment decoder. Equipments Required Bread board IC7404,IC7410, IC7408,IC 7432 Connecting wires Power supply Quantity 1 1 Each As required 1

Procedure: 1. 2. 3. In a breadboard, the connections are made as per the circuit diagram +5v is given to 14th pin and 7th pin given the ground. The input values are given and the corresponding output values are verified as per the truth table.

X 0 0 0 0 1 1 1 1

INPUT Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

TRUTH TABLE FOR ENCODER OUTPUT D0 D1 D2 D3 D4 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D5 0 0 0 0 0 1 0 0

D6 0 0 0 0 0 0 1 0

D7 0 0 0 0 0 0 0 1

TRUTH TABLE FOR DECODER

D0 1 0 0 0 0 0 0 0

D1 0 1 0 0 0 0 0 0 RESULT:

D2 0 0 1 0 0 0 0 0

INPUT D3 D4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0

D5 0 0 0 0 0 1 0 0

D6 0 0 0 0 0 0 1 0

D7 0 0 0 0 0 0 0 1

X 0 0 0 0 1 1 1 1

OUTPUT Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

EX NO:7 DATE:

2 BIT AND 8-BIT MAGNITUDE COMPARATOR

Aim: 1. To construct a 8-bit magnitude comparator using IC7485 . 2. To design, construct and verify the truth table of TWO-BIT MAGNITUDE
COMPARATOR.

Equipments Required: Equipment Breadboard 4-bit Magnitude comparator Power supply AND gate OR gate NOT gate EX-OR gate Connecting wires Theory: Range IC7485 0-5 V IC7408 IC7432 IC7404 IC7486 Quantity 1 2 1 2 1 1 1 As needed

TWO-BIT MAGNITUDE COMPARATOR. The two bit magnitude comparator can be constructed using the logic gates as shown. The inputs are 2 two bit numbers. If the inputs are same the output of (A=B) is HIGH and all others are low. If any one of the input is greater then the output of that corresponding input will be HIGH. For example, if A is greater than B then, the output of (A>B) will be HIGH and vice-versa. Thus a basic circuit which compares the two inputs and generates the output is designed and its truth tables are verified.

Truth table:
INPUTS A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 OUTPUTS A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

Figure 2 BIT MAGNITUDE COMPARATOR

4-BIT MAGNITUDE COMPARATOR The IC7485 is a 4-bit magnitude comparator that can be expanded to almost any length, It compares two 4-bit binary, BCD or other monotonic codes and presents the three possible magnitude results at the outputs. There are two expansion schemes available; they are series expansion and parallel expansion

Pin diagram:

B3 I(A<B) I(A=B) I(A>B) A>B A=B A<B


GND

1 2 3 4 5 6 7 8

16 15 14

IC7485

13 12 11 10 9

VCC A3 B2 A2 A1 B1 A0 B0

LOGIC DIAGRAM FOR 8 BIT MAGNITUDE COMPARATOR:


MSB Input A MSB Input B LSB Input A LSB Input B +5V A 3 A2 A1 A0 Output A>B A=B A<B IC7485 B3 B2 B1 B0 I(A>B) I(A=B) I(A<B) A3 A2 A 1 A0 A>B A=B A<B IC7485 B3 B2 B1 B0 I(A>B) I(A=B) I(A<B)

GND

Procedure: Place the ICs carefully on the breadboard. Connect the 16th pin to the supply and 8th pin to the ground. Switch on and off the corresponding switches of the input variables and check for the output. RESULT:

EX NO: 8 DATE: Aim:

STUDY OF FLIP FLOPS

To design and study the following flip flops. i) RS flip flop ii) clocked RS flip flop iii) D flip flop iv) JK flip-flop v) T- flip flop. Apparatus required: Bread board , IC 7402, IC 7400, IC 7408, IC 7404, IC 7411,power supply, wires. Theory: A flip flop circuit can maintain a binary state indefinitely until directly by an input signal to switch states. 1) SR latch: It is called direct coupled RS flip flop and is constructed by using 2 NAND gates. It has two inputs and two outputs. 2) Clocked RS flip flop: By adding gates to the inputs of the logic circuit, flip flop can be made to inputs levels during occurrence of clock pulses. This flip flop contains NOR and AND gates and it is a three input and two output flip flop. 3) D flip flop: It is an RS flip flop with an inverter on the R output, thus the input is reduced to one. The clock input is often given to variable designation CP or CL to indicate their input enables gated latch to make data entry possible into the flip flop. It is a two input and two output flip flop. 4) JK flip flop: It is a refinement of RS flip flop. The inputs J and K behave like S and R to set and clear the flip flop. It has NOR and AND gate. It is a three input and two output flip flop. 5) T flip flop: It is a single input version of the JK flip flop. It is a two input and two output flip flop. It contains AND and NOR gates.

SR FLIP FLOP: LOGIC DIAGRAM:

i)USING NOR GATE: CIRCUIT DIAGRAM:

STATE TABLE: INPUTS S 0 0 1 1 R 0 1 0 1 OUTPUTS Q Q 0 1 1 0 0 1 0 0

STATE No change Set Reset indeterminate

ii) CLOCKED SR FLIP FLOP:

LOGIC DIAGRAM:

CIRCIUT DIAGRAM:

STATE TABLE:

CP 0 0 0 0 1 1 1 1

S 0 0 1 1 0 0 1 1

R 0 1 0 1 0 1 0 1

Q 0 0 0 0 0 0 1 1/0

Q 1 1 1 1 1 1 0 1/0

STATE No change No change No change No change No change Reset Set Indeterminate

iii) D flip flop: Logic diagram:

Circuit diagram:

Clk

State diagram:

INPUTS CP 1 1 D 0 1

OUTPUTS Q 0 1 Q 1 0

iv) JK FLIP FLOP: LOGIC DIAGRAM:

CIRCIUT DIAGRAM:

Clk

STATE TABLE: INPUTS Q(t) 0 0 0 0 1 1 1 1 J 0 0 1 1 0 0 1 1 K 0 1 0 1 0 1 0 1 OUTPUT Q(t+1) 0 0 1 1 0 1 1 0

v) T FLIP FLOP: LOGIC DIAGRAM: T Q

>C

CIRCUIT DIAGRAM:

T Clk

STATE TABLE: PRESENT STATE Q 0 0 1 1 INTPUT T 0 1 0 1 OUTPUT Q(t+1) 0 1 1 0

RESULTS:

EX NO: 9 DATE: DESIGN AND IMPLEMENTATION OF COUNTERS USING FLIP FLOPS. Aim: 1. To Design and implement binary ripple counter using flip flops. 2. To design and implement a synchronous decade counter using T-flip flop. Sl.No. 01. 02. 03. 04. Equipments Required IC7476,IC7411, IC7404, IC7408 ,IC7432 Bread board Power supply Connecting wires Quantity 2 1 1 As required

Theory: Binary ripple counter: A register that goes through a prescribed sequence of states upon the application of input process is called a counter. The input pulses may be clock pulses or they may originate from some external source and may occur at fixed intervals of time. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the C input of some or all flipflops are triggered not by common clock pulses but rather by transition that occurs in other flipflops outputs. A binary ripple counter consists of series connection of complementing flipflops with output of each flipflop connected to the C input of next higher order flipflop. The flipflop the least significant bit receives the incoming count pulses. It is implemented with a JK or T or D flipflop.

Synchronous decade counter: Synchronous decade counter is a sequential circuit. These circuits have memory elements because the output depends upon past output and present inputs. Synchronous decade counter is used to count from 0 to 9 repeatedly. Synchronous decade counter can be designed using any flip flop. Here the present state consists of a variables. In the case of D flip flop one input is the compliment of the other.

Procedure: i. ii. iii. Connections are made as per circuit diagram on a Bread board. Connect the supply inputs The input is applied and output is verified.

CLK 0 1 2 3 4 5 6 7 8 FUNCTION TABLE

BINARY DECIMAL CELL 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 000

PRESENT 0 1 0 1 1 1 1

INPUT CLEAR 1 0 0 1 1 1 1

CLOCK X X X 1 1 1 1

J X X X 0 0 1 1

K X X X 0 1 0 1

OUTPUT Q Q' 1 0 0 1 1 1 NO CHANGE 0 1 1 0 TOGGLE

COUNT SEQUENCE A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 Conditions for complementing FFS complement A1 complement A1,A1 will go from 1 to 0 and complement A2 complement A1 complement A1,A1 will go from 1 to 0 and complement A2 .A2 will go from 1 to 0 and complement A3. complement A1 complement A1,A1 will go from 1 to 0 and complement A2 complement A1 complement A1,A1 will go from 1 to 0 and complement A2 and so on

Pin out Details of JK flip flop: 7476 Dual J-K Flip Flops

J1
14

Q1
13

Q1
12

GND
11

K2
10

Q2
9

Q2
8

IC 7473

Clk

Clr

K1

Vcc

Clk

Clr

J2

Synchronous decade counter: (Using T- Flip Flop) State diagram:

0000 0001 1001 1000

0010

0011 0100 0101 0110

0111

State Table: Present State B C D 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 Next State Excitation Inputs (T-FF) A(t+1) B(t+1) C(t+1) D(t+1) TA TB TC TD 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1

A 0 0 0 0 0 0 0 0 1 1

K-Map Simplification:

QB QA QD QC 00 01 11 10 1 d d 1 d d d d 00 01 11 10

TA=QAQBQC+QAQD

QB QA QD QC 00 01 11 10 d d 00 01 11 1 1 d d d d 10

TC=QAQB
QB QA QD QC 00 01 11 10 00 01 1 1 d d 11 1 1 d d 10

d TA=QAQD

QB QA QD QC 00 01 11 10 00 1 1 d 1 01 1 1 d 1 TA=1 11 1 1 d d 10 1 1 d d

Circuit Diagram: ( T-FF realized using JK-FF)


QA QB QC QD

TA

QA

TB

QB

TC

QC

TD

QD

Clk QD

RESULT:

EX NO: 10 DATE: DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS Aim: To design different types of shift registers like serial in serial out ,serial in parallel out,parallel in parallel out and parallel in serial out using d flip flop. Apparatus required: IC7408 , IC7432 , IC7474, Bread board. Theory: A register capable of shifting its binary information either to the right or to the left is called a shift register .It consists of a chain of flipflops in cascade with output of one flipflop as the input of the next flipflop .A the flipflops receive a common clock pulse. The common clock pulse causes shift registers to move from one state to the next.

Procedure: Connect the circuit as per the circuit diagram. ICs are firmly placed on the bread board of the trainer kit. The supply votage and ground connections are properly given. Checking is made to see if proper turnsare given as per the truth table.

SI

Q0

Q1

Q2

Q3

SO

SERIAL IN SERIAL OUT

OBSERVATION TABLE INPUT SI TIMING PULSE SHIFT REGISTER Q1 Q2 Q3 SERIAL OUTPUT

Q0

OBSERVATION TABLE

SERIAL IN PARALLEL OUT

Q0 SI D Q0 D

Q1 D Q2

Q2 D Q3

Q3

INPUT

TIMING PULSE

Q0

SHIFT REGISTER Q1 Q2 Q3

B C PARALLEL IN PARALLEL OUT D Q D Q D Q

D D Q

TIMING PULSE INITIAL VALUE CLOCK PULSE

INPUT A B C D

OUTPUT QA QB QC QD

14 13 12 11

10 9

8 PIN

IC 7474

DIAGRAM FO R D FLIP FLO P

PARALLEL IN SERIAL OUT SHIFT/LOAD


B C D

A D QA D QB D QC D QD SO

CLOCK

SHIFT/ TIMING LOAD PULSE

SHIFT REGISTER A B C

OUTPUT D

RESULT:.

Appendix
I. Clock Generator IC 555 Timer Pin connections

The 555 timer is an extremely versatile integrated circuit which can be used to build lots of different circuits.

. Astable circuits Astable circuits produce pulses. The circuit most people use to make a 555 astable looks like this:

As you can see, the frequency, or repetition rate, of the output pulses is determined by the values of two resistors, R1 and R2 and by the timing capacitor, C.

The design formula for the frequency of the pulses is:

The HIGH and LOW times of each pulse can be calculated from:

The duty cycle of the waveform, usually expressed as a percentage, is given by:

II . Introduction to ORCAD/PSPICE
ORCAD is a schematic editor. In other words, it is a program that allows you to draw circuit schematics. PSPICE is an electrical simulator that allows you to simulate the operation of the circuits whose schematic you prepared using ORCAD. This allows students to check for correct circuit operation even before they actually construct the circuit in lab. Steps in PSPICE using ORCAD schematic editor with Voltage Divider Example: Launch the ORCAD schematic editor by double-clicking on the ORCAD icon.

Click on File from the main menu bar and then select Open New Project. You should then see the following dialog box.

Enter the name of the project "tutorial" and also enter the Location of the folder where the schematics and your simulation results will be saved. Use the Browse button to select the location where you would like to save your files. Make sure the Analog or Mixed A/D option has been selected. You may then click the OK button. The following dialog box will appear.

Make sure to select Create a blank project and then click the OK button.

Let's create a simple voltage divider i.e. two resistors, each with a value of 10KW. We will drive the series combination with a sinusoid and observe the voltage at the node between the two resistors. Voltage division principles tell us that the voltage should be half of the input voltage. From the menu at the top, select Place and then Part (Shift-P if you wish can be used as a shortcut). The following dialog box will appear.

Click on the Add Library button and choose the ANALOG library. You will see the following.

Select the R i.e. resistor component. This can be done by double clicking on the R. Place the component by clicking somewhere near the middle of the schematic page.

Click again and place R2. You should then hit the Esc key to exit the place mode. The resistor R2 should still be selected as is shown on the next page.

With resistor R2 selected, right mouse click on it. A menu will appear. Select the Rotate option. You should observe the following.

Right mouse click on the 1k value on the R1 component. A menu will appear. Select Edit Properties. The dialog box shown below will appear. Change the value to 10K.

Do the same for the R2 component. At this point we should probably save our work. This can be done by either typing Ctrl-S or by clicking on the diskette icon in the toolbar or by going to the File menu and selecting Save. Do a Place Part again. This time add the Source library, From the Source library, select VSIN. Place the sinewave generator and change the parameter values. VOFF should be 0. VAMPL should be set to 1. FREQ should be set to 1k.

Now place the ground symbol. Choose Place and Ground. Let's use the GND/CAPSYM symbol.

In order for PSPICE to simulate the circuit correctly, we must change the name of the GND symbol from GND to 0. This is because in all versions of SPICE, circuit ground must always be assigned a nodename of 0. We can do this by selecting the GND symbol. Now, right mouse click on the symbol. A menu will pop up. Select the Edit Properties option. In the Name field where it says GND, change this to 0 as I have done below. Use a right mouse click on the Name field to highlight the field and click on display. The Display Properties dialog box will appear.

Your circuit should look like the figure below.

It is now time to wire the components to one another. This can be done by placing a wire. Place Wire and Shift-w is the shortcut! Click on a pin then drag to mouse to another pin and click again. When the components are all wired together, leave the wiring mode by hitting the Esc key. Your circuit should look like mine below.

We now are ready to simulate the circuit. We must first prepare a simulation profile where we describe how we want the simulation to be performed. To do this select Pspice menu and then New Simulation Profile. The following dialog box appears. I have entered a name for the simulation. I decided to call it tran. You may call it anything you wish. Click on the Create button to create the profile.

After clicking on the Create button, the following dialog box will appear. Since the input frequency is 1 kHz which has a corresponding period of 1 ms, I have decided to run for 5 ms i.e. 5 periods of the waveform. I also desire 100 data points per period of the sinusoid so I have indicated that the maximum step size be 10 ms (1 ms / 100 = 10 ms)

We also need to tell PSPICE which nodes we would like to plot. We do this by going to the main menubar and selecting PSpice. We then select Markers and Voltage. We place the marker on the output of the voltage divider as shown below.

For comparison purposes, let's also place a marker on the input node as illustrated in the figure below.

At this point we should probably save our work. This can be done by either typing Ctrl-S or by clicking on the diskette icon in the toolbar or by going to the File menu and selecting Save. We are now ready to run the PSPICE simulation. We do this by selecting PSpice from the main menubar and then Run. We could also click on the the arrow icon on the toolbar. After a few seconds another window will open and you will see the following simulation traces.

Notice the green trace (output) has one-half the amplitude of the red trace (input) as we predicted. Similarly we can do digital simulation also.

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