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r05311403 Switching Theory and Logic Design

r05311403 Switching Theory and Logic Design

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07/13/2010

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Code No: R05311403
Set No. 1
III B.Tech I Semester Regular Examinations, November 2007SWITCHING THEORY AND LOGIC DESIGN(Mechatronics)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆ ⋆ ⋆ ⋆ ⋆
1. Convert the following to Decimal and then to Hexadecimal.(a) 3214
8
(b) 4567
8
(c) 10101101
2
(d) 1100101
2
(e) 756
10
(f) 533
10
[3+3+3+3+2+2]2. (a) Express the following functions in sum of minterms and product of maxterms.[8]i. (xy + z) ( y + xz)ii. B’D + A’D + BD(b) Obtain the complement of the following Boolean expressions. [8]i. AB’C + AB’D + A’B’ii. A’B’C + ABC? + A’B’C’Diii. ABCD + ABC’D’ + A’B’CDiv. AB + ABC’3. Minimize the the following multiple output functions.
1
=
m
(0
,
2
,
6
,
10
,
11
,
12
,
13) +
d
(3
,
4
,
5
,
14
,
15)
2
=
m
(1
,
2
,
6
,
7
,
8
,
13
,
14
,
15) +
d
(3
,
5
,
12). [16]4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Fulladder. [8+8]5. (a) List the PLA programming table for the BCD to excess-3 code converter.(b) A ROM chip of 4,096 x 8 bits has two clip select inputs and operates froma 5-volt power supply. How many pins are needed for the integrated circuitpackage? Draw the block diagram of this ROM. [8+8]6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.(b) Compare synchronous & Asynchronous. [10+6]1 of 2

Code No: R05311403
Set No. 1
7. A clocked sequential circuit is provided with a single input x and single output Z.Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of thesequence it produce an output Z = 1 and overlapping is also allowed.(a) Obtain State - Diagram.(b) Also obtain state - Table.(c) Find equivalence classes using partition method & design the circuit using D- ip-ops. [4+4+8]8. (a) Draw the ASM chart for the following state transistion, start from the initialstate
1
, then if xy=00 go to
2
, if xy=01 go to
3
, if xy=10 go to
1
, otherwise go to
3
.(b) Show the exit paths in an ASM block for all binary combinations of controlvariables x, y and z, starting from an initial state. [8+8]
⋆ ⋆ ⋆ ⋆ ⋆
2 of 2

Code No: R05311403
Set No. 2
III B.Tech I Semester Regular Examinations, November 2007SWITCHING THEORY AND LOGIC DESIGN(Mechatronics)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆⋆⋆⋆⋆
1. Convert the following to Binary and then to gray code.(a) 1010
16
(b)
AB
33
16
(c) 3323
8
(d) 1764
8
(e) 187
10
(f) 2266
10
[2+2+2+2+4+4]2. (a) Reduce the following Boolean expressions. [8]i. B ‘C’D + (B + C + D)’ + B’C’D’Eii. AB + (AC)’ + AB’C(AB + C)iii. A’B’C’ + A’BC’ + AB’C’ + ABC’iv. A + B + A’B’C(b) Obtain the complement of the following Boolean expressions. [8]i. x’y’ + xy + x’yii. xy’ + y’z’ + x’z’iii. x? + xy + xz’ + xy’z’iv. (x + y)(x + y’)3. (a) Explain ,the determination of all possible minimal expressions from a reducedprime implicant chart. [8](b) Make a K-map of the following expression and obtain the minimal SOPandPOS forms. (
A
¯
) + (
AB
) + (
) + (
) + (
A
¯
BC
) + (
ABC
). [8]4. Implement the following Boolean function by a Hazard free OR-AND network.
=
m
(3
,
4
,
5
,
7) and explain in detail what are the Hazards encountered inimplementing the above function. [16]5. (a) Derive the PLA programming table for the combinational circuit that squaresa 3 bit number.1 of 2