Rr220501 Computer Organization

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Code No: RR220501

Set No. 1

II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007COMPUTER ORGANIZATION( Common to Computer Science & Engineering, Information Technology,Computer Science & Systems Engineering and Electronics & ComputerEngineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks

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1. (a) What is instruction Cycle ?(b) Elaborate the characteristics of a hypothetical machine(c) What do you mean by hardwired program? [6+6+4]2. (a) What is BCD representation. List the advantages of it.(b) Convert the following binary numbers to decimal and octal formsi. 101101110ii. 1.011101 [8+8]3. (a) Discuss various aspects of instruction set design.(b) Explain about various types of data on which machine instructions operate.[10+6]4. (a) List the characteristics of superscalar processors and contrast it with CISCprocessors.(b) Explain the instruction execution characteristics of RISC processors.(c) What is semantic gap problem? [6+6+4]5. (a) Discuss about principles of cache memory.(b) Elaborate on elements of cache memory.(c) Explain the purpose of replacement algorithms [6+5+5]6. (a) List the hardware events that occur after an I/O device completes an I/Ooperation in interrupt driven I/O.(b) List and explain the interrupt modes of Intel 8259A interrupt controller.[8+8]7. (a) List and explain the functions of control unit(b) What is sequencing logic unit? Explain it’s purpose. [8+8]8. (a) Diﬀerentiate between miltiprocessors and multicomputers.(b) Discuss about instruction pipeline. [7+9]

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Code No: RR220501

Set No. 2

II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007COMPUTER ORGANIZATION( Common to Computer Science & Engineering, Information Technology,Computer Science & Systems Engineering and Electronics & ComputerEngineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks

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1. (a) How optional signal lines for PCI are functionally grouped .(b) Explain typical server system using PCI configuration. [8+8]2. (a) What is BCD representation. List the advantages of it.(b) Convert the following binary numbers to decimal and octal formsi. 101101110ii. 1.011101 [8+8]3. List branch oriented, load/store and floating point operation of power PC withdescription [16]4. (a) Give weighted relative dynamic frequency of HLL operations(b) What do you mean by dynamic percentage of operands?(c) Discuss about overlapping register windows [6+5+5]5. (a) Differentiate between single versus two-level caches.(b) Elaborate on Pentium Cache Organization. [8+8]6. (a) List the hardware events that occur after an I/O device completes an I/Ooperation in interrupt driven I/O.(b) List and explain the interrupt modes of Intel 8259A interrupt controller.[8+8]7. (a) List and explain the functions of control unit(b) What is sequencing logic unit? Explain it’s purpose. [8+8]8. (a) Give a summary of arithmetic and logical operations that are defined for thevector architecture.(b) What is cache coherence problem. Discuss about different cache coheranceapproches. [8+8]

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Code No: RR220501

Set No. 3

II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007COMPUTER ORGANIZATION( Common to Computer Science & Engineering, Information Technology,Computer Science & Systems Engineering and Electronics & ComputerEngineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks

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1. (a) Explain the purpose and merits of interrupts.(b) Draw and explain the instruction cycle with interrupts.(c) What is interrupt handler? Explain its purpose. [6+6+4]2. (a) What do you mean by improper storage of ﬂoating point numbers. Explainwith an example.(b) What is the range of real numbers represented in normalized ﬂoating pointrepresentation in a 6 digit register. [8+8]3. (a) What is big-endian and little-endian address mapping(b) List points favoring big-endian and little-endian styles.(c) What is bit ordering? [6+6+4]4. (a) Explain about the machine state register.(b) List the characteristics of CISC and RISC processors [8+8]5. (a) Explain the operation of a static RAM cell.(b) Explain the internal organization of 1M

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1 dynamic memory chip.(c) How should you build 64K

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8 memory module using 16K

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1 static memorychips. [4+6+6]6. (a) What is multiple-platter disk.(b) Differentiate between fixed and movable head disks.(c) Define ‘disk access time’, ‘seek time’ and ‘rotational latency’.[5+5+6]7. Discuss about horizontal and vertical instruction formats. Also differentiate be-tween horizontal and vertical instruction formats. [16]8. (a) Discuss about addressing modes sutiable for a pipelined processor.(b) Differentiate between complex and simple addressing modes in a pipeline(c) What is multiple execution unit. Explain their functioning and uses.[6+4+6]

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