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Code No: A0611 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech I Semester Regular Examinations March/April 2010 LOW POWER VLSI DESIGN
(COMMON TO DIGITAL SYSTEMS & COMPUTER ELECTRONICS, WIRELESS & MOBILE COMMUNICATION)

NR

Time: 3hours Answer any five questions All questions carry equal marks --1. a) b) 2. a) b) 3. a) b)

Max.Marks:60

Explain about full custom design approach and gate array approach, in VLSI circuit design and compare them with standard- cell approach. Explain about SOI technology. What are the advantages of the same? Draw the structure of standard buried collector (SBC), BICMOS with a buried n+ layer and explain the same. What is short channel effect? Explain how punch-through is avoided? With the help of a neat sketch, explain about Shallow Trench Isolation Technique. What are its advantages? Give the cross sectional schematic view of standard LOCO s process and explain the same. List the various steps involved in Analog/Digital BICMOS process and explain the same. Explain about level 1 and level 2 model parameters and equations pertaining to SPICE models of MOSFETs with the help of necessary graphs. Draw the circuit for BICMOS buffer and explain the operation of the same. Draw the circuit and structure for a merged BICMOS configuration and explain the same. Draw the logic circuit for Quasi-complimentary BICMOS digital circuit and explain about its operation. Derive the expression for Turn-ON or Fall Time of CMOS Inverter considering different states of LOAD MOSFET. Write short notes on any TWO a) Quality Measures for Latches. b) ESD-free Bi CMOS. c) Pipelining Theme is low power FFs.

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