Q1. What are the limitations of 8 bit microprocessor?

Ans: Limitations of 8 bit microprocessor: 8-bit microprocessors are those which have 8-bit central processing unit. Eight-bit CPU normally uses an 8-bit data bus and a 16-bit address bus which means that their address space is limited to 64 KB (220 byte). 16 bit or more are processed by making the groups of 8 bit. Eight-bit architecture; many applications require greater precision than is provided by eight bits. Analogue data is usually represented by 12-14 bits. While multi-byte arithmetic is possible it immediately introduces a large reduction in speed. Limited address space; The 8-bit address bus limits memory space to 32kBytes. This can be increased using bank switching but this is not an elegant solution and still limits the size of individual programs. It is not uncommon for computer systems to have 8MBytes of memory now that reductions in cost of memory devices have made this economic. Limited address registers; only having 2 address registers can be a problem where manipulating tables of data is concerned. Limited number of data registers; only having 2 data registers means that data being manipulated often resides in memory. The resulting memory accesses degrade the performance. ---------------------------------------------Q2. Compare the 8 bit microprocessors 8080A and 8085? Ans: FEATURES Description 8085 It is an 8 bit microprocessor. 8080A

The Intel 8080 was the second 8-bit microprocessor designed It is manufactured with N-MOS and manufactured. technology. As in many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them It uses the same basic instruction set as the 8008 and source code compatible with its predecessor, but added some handy 16-bit operations to the instruction set as well. The

Programming model

are followed by one or two bytes of data, which could be an immediate operand, a memory address, or a port number. Registers The processor has seven 8-bit registers accessible to the programmer, named A, B, C, D, E, H, and L. Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL could be accessed as pseudo register M. Like larger processors, it has CALL and RETS instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit registerpair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at the fixed addresses 00h, 08h, 10h, and 38h. Most 8-bit operations work on the 8-bit accumulator. Due to the regular encoding of the MOV-instruction (using a quarter of available opcode space) there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except

8080's large 40-pin DIP packaging permitted it to provide a 16-bit address bus and an 8-bit data bus, allowing easy access to 64 kilobytes of memory. The processor has seven 8-bit registers, (A, B, C, D, E, H, and L) where A is the 8-bit accumulator and the other six could be used as either byteregisters or as three 16-bit register pairs (BC, DE, HL) depending on the particular instruction. As with many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which could be an immediate operand, a memory address, or a port number.

Commands/instructions

8-bit instructions

Most 8-bit operations can only be performed on the 8-bit accumulator (the A register). For dyadic 8-bit operations, i.e. 8-bit operations with two operands, the other operand could be either an immediate value, another 8-bit register, or a memory cell addressed by the

for delays. 16-bit operations Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps. Operations that have to be implemented by program code (subroutine libraries) included comparisons of signed integers as well as multiply and divide.

16-bit register pair HL Although the 8080 is generally an 8-bit processor, it also have limited abilities to perform 16bit operations: Any of the three 16-bit register pairs (BC, DE, HL) or SP can be loaded with an immediate 16-bit value , incremented or decremented. By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction

---------------------------------------------Q3 Why address bus is unidirectional and data bus is bidirectional? Ans: ADDRESS BUS The address bus unidirectional because the address is transferred only between the cpu and memory. High Order An address bus is a computer bus (a series of lines connecting two or more devices) that is used to specify a physical address. When a processor or DMA-enabled device needs to read or write to a memory location, it specifies that memory location on the address bus (the value to be read or written is sent on the data bus). DATA BUS Data bus is bidirectional because it transfers information between processor/controller and memory device. Low Order A Data Bus is a subsystem that transfers data between computer components inside a computer or between computers. Connects all the internal components of a computer, such as CPU and memory, to the motherboard.

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Q4

(a) How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? Ans (a): 128 x 8 RAM => 128 Bytes (8bits) / chip => Number of chips = 2048 / 128 = 16 Therefore, 16 chips are needed to provide a memory capacity of 2048 bytes. (b) How many lines of the address bus must be used to access 2048 bytes of memory? How many these lines will be common to all chips? Ans (b): 2048 = 2d, Where d is number of address lines => d = 11. We have 16 chips => 4 bits for chip select. Number of common address lines is 11 - 4 = 7 Summary: 4 bits to select the correct chip and 7 bits to select the memory location inside the selected chip.

(c) How many lines must be decoded for chip select? Specify the size of decoder. 2048. Ans(c): We need 4 * 16 line decoder. Since we have 16 chips, we need 4 (24 = 16) address lines decoded to select the right chip. 4 lines to address chips + 7 address lines to address 128 bytes = 11 address lines all together. ----------------------------------------------

Q5. Write instructions to load the hexadecimal numbers 65H in register C, and 92h in the accumulator A .Display the number 65H at PORT0 and 92H at PORT1? Ans: MVI C, 65H MVI A, 92H OUT PORT1; DISPLAY 92H MOV A, C; COPY C INTO A FOR DISPLAY OUT PORT0; DISPLAY 65H HLT ---------------------------------------------Q6. Why the number of out ports in the peripheral-mapped I/O is restricted to 256 ports? Ans: The number of output ports in the peripheral I/O is restricted to 256 ports because the operand of the OUT instruction is 8-bits; it can have only 256 combinations. 28=256.

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