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TMS320F2812 - Digital I/O

TMS320F2812 - Digital I/O

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Published by: Pantech ProLabs India Pvt Ltd on Sep 19, 2012
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DSP28 - Digital I/O 3 - 1
Introduction
This module introduces the integrated peripherals of the C28x DSP. We have not only a 32-bitDSP core, but also all of the peripheral units needed to build a single chip control system (SOC -“System on Chip”). These integrated peripherals give the C28x an important advantage over other  processors.We will start with the simplest peripheral unit – Digital I/O. At the end of this chapter we willexercise input lines (switches, buttons) and output lines (LED’s).
Data Memory Mapped Peripherals
All the peripheral units of the C28x are memory mapped into the data memory space of its Harvard Architecture Machine. This means that we control peripheral units byaccessing dedicated data memory addresses. The following slide shows these units:
33--22
C281x Block DiagramC281x Block Diagram
32x32 bitMultiplier 
 
32x32 bit32x32 bitMultiplier Multiplier SectoredFlash
 
SectoredSectoredFlashFlashA(18A(18--0)0)D(15D(15--0)0)Program BusProgram BusData BusData BusRAM
 
RAMRAMBootROM
 
BootBootROMROM2222
32-bitAuxiliaryRegisters
 
3232--bitbitAuxiliaryAuxiliaryRegistersRegisters
332 bitTimers
 
3332 bit32 bitTimersTimersRealtimeJTAG
 
RealtimeRealtimeJTAGJTAGCPUCPURegister BusRegister BusR-M-WAtomicALU
 
RR--MM--WWAtomicAtomicALUALUPIEPIEInterruptInterruptManager Manager 323232323232EventManager A
 
EventEventManager AManager AEventManager B
 
EventEventManager BManager B12-bit ADC
 
1212--bit ADCbit ADCWatchdog
 
WatchdogWatchdogMcBSP
 
McBSPMcBSPCAN2.0B
 
CAN2.0BCAN2.0BSCI-A
 
SCISCI--AASCI-B
 
SCISCI--BBSPI
 
SPISPIGPIO
 
GPIOGPIO
 
Digital I/O
 
Module Topics3 - 2 DSP28 - Digital I/O
Module Topics
Digital I/O...................................................................................................................................................3-1
 
 Introduction .............................................................................................................................................3-1
 
 Data Memory Mapped Peripherals .........................................................................................................3-1
 
 Module Topics..........................................................................................................................................3-2
 
The Peripheral Frames............................................................................................................................3-3
 
 Digital I/O Unit........................................................................................................................................3-4
 
 Digital I/O Registers................................................................................................................................3-6 
 
C28x Clock Module..................................................................................................................................3-7 
 
Watchdog Timer.......................................................................................................................................3-9
 
System Control and Status Register.......................................................................................................3-12
 
 Low Power Mode...................................................................................................................................3-12
 
 Lab 2: Digital Output – 8 LED’s...........................................................................................................3-15
 
 Lab 2A: Digital Output – 8 LED’s (modified) .......................................................................................3-22
 
 Lab 3: Digital Input...............................................................................................................................3-23
 
 Lab 3A: Digital Input + Output.............................................................................................................3-26 
 
 Lab 3B: Start / Stop Option....................................................................................................................3-29
 
 
The Peripheral FramesDSP28 - Digital I/O 3 - 3
The Peripheral Frames
All peripheral registers are grouped together into what are known as “Peripheral Frames” – PF0,PF1 and PF2.These frames are data memory mapped only. Peripheral Frame PF0 includesregister sets to control the internal speed of the FLASH memory, as well as the access timing tothe internal SARAM. SARAM stands for “Single Access RAM”, that means we can make oneaccess to this type of memory per clock cycle. Flash is the internal non-volatile memory, usuallyused for code storage and for data that must be present at boot time. Peripheral Frame PF1contains most of the peripheral unit control registers, whereas Peripheral Frame PF2 is reservedfor the CAN register block. CAN – “Controller Area Network” is a well-established network widely used inside cars to build a network between electronic control units (ECU).
3 -3
TMS320F2812 Memory Map
MO SARAM (1K)M1 SARAM (1K)LO SARAM (4K)L1 SARAM (4K)HO SARAM (8K)Boot ROM (4K)
MP/MC=0
BROM vector (32)
MP/MC=0 ENPIE=0
OTP (2K)FLASH (128K)
reservedreservedreservedPF 0 (2K)reservedreservedPF 1 (4K)reservedPF 2 (4K)reservedPIE vector (256)ENPIE=1XINT Zone 0 (8K)XINT Zone 1 (8K)XINT Zone 2 (0.5M)XINT Zone 6 (1M)XINT Zone 7 (16K)MP/MC=1XINT Vector-RAM (32)MP/MC=1 ENPIE=0reservedreservedreserved
Data | Program
00 000000 040000 080000 0D0000 100000 600000 700000 800000 900000 A0003D 78003D 80003F 80003F A0003F F0003F FFC03F C00020 000010 000008 000000 400000 2000
Data | Program128-Bit Password
CSM: LO, L1OTP, FLASH
 Some of the memory areas are password protected by the “Code Security Module” (check  patterned areas at the slide above). This is a feature to prevent reverse engineering. Once the password area is programmed, any access to the secured areas is only granted when the correct password is entered into a special area of PF0. Now let’s start with the discussion of the Digital I/O unit.

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