Introduction

ECE6133 Physical Design Automation of VLSI Systems Prof. Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology

Design and Fabrication of VLSI Devices

Objectives:

To study the materials used in fabrication of VLSI devices. To study the structure of devices and process involved in fabricating different types of VLSI circuits

Fabrication Materials

MOS Subthreshold Region

Subthreshold Region I ds 0 , V gs V

Subthreshold current is due to reverse bias leakage current of diode between diffusion and substrate

ECE 3060

Lecture 23

MOS Linear Region

The inversion layer (channel) is symmetric, until:

2 V ds I ds = ( V gs V t )V ds -------2

O V ds V gs V t

ECE 3060

Lecture 24

MOS Linear Region

Transverse electric eld distorts the channel

2 V ds I ds = ( V gs V t )V ds -------2

O V ds V gs V t

ECE 3060

Lecture 25

MOS Saturation Region

Channel is pinched off when V gs V t V ds

Current is swept through depletion region electric eld after leaving channel.
ECE 3060 Lecture 26

Fabrication of VLSI Circuits

1. Create 2. Define 3. Etch
Silicon wafers

Material formation by deposition, diffusion or implantation

Pattern definition by photolithography

Etch
8 to 10 iterations

Photolithographic Process
UV Radiation Silicon dioxide Photoresist (Negative ) Silicon

Shadow of mask feature (a) Hardened Photoresist (b)

Photo mask with opaque feature

(c) Photoresist stripped

(d)

Silicon dioxide etched where exposed

(e)

Design Rules
Minimum Separation [A]
Intralayer (all layers) Interlayer (active to poly/well/select) From Transistor

Minimum Width (all layers) [B] Minimum Overlap [C]

Past Transistor (poly, active) Around Contact Cut (all contacted layers) Around Active (well, select)

Exact Size (contact cuts) [D]

ECE 3060

Lecture 313

Width/Spacing Design Rules

ECE 3060

Lecture 315

A CMOS Inverter

A CMOS NAND Gate

A CMOS NOR Gate

VLSI Physical Design Automation

VLSI Design Cylce

manual System Specifications

Chip

automation

Large number of devices Optimization requirements for high performance Time-to-market competition Cost

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ECE6133: Physical Design Automation of VLSI Systems

Sample Automatic Layout

matrix solver multiply-accumulate (MAC) unit 32-bit processor

Prof. Sung Kyu Lim, Georgia Institute of Technology

Matrix Solver (20K)

Cadence Encounter: placement (1 sec), routing (12 sec)
Area = 72x72um (45nm library), used 6 metal layers

Matrix Solver (20K)

M1

M2

M3

M4

M5

M6

Matrix Solver (20K)

GDSII shots: manufacturing-ready
Used Cadence Virtuoso, passed DRC

Matrix Solver (20K)

GDSII shots: manufacturing-ready
Specify all intra-cell details

MAC Unit (267K)

Placement took 44 sec, routing took 289 sec
Area = 320x320um, used 7 metal layers

MAC Unit (267K)

M1

M2

M3

M4

M5

M6

MAC Unit (267K)

M7

MAC Unit (267K)

Placement

Routing

MAC Unit (267K)

32-bit Processor (2.7M)

Placement took 739 sec, routing took 4740 sec
Area = 1000x1000um, used 10 metal layers

32-bit Processor (2.7M)

M1

M2

M3

M4

M5

M6

32-bit Processor (2.7M)

M7

M8

M9

M10

Placement Comparison
Runtime: 1 sec vs 44 sec vs 739 sec

20K

267K

2.7M

Routing Comparison
Runtime: 12 sec vs 289 sec vs 4740 sec

20K

267K

2.7M

VLSI Physical Design Automation

VLSI Design Cycle

1. System Speci cation 2. Functional Design 3. Logic Design 4. Circuit Design 5. Physical Design 6. Design Veri cation 7. Fabrication 8. Packaging, Testing, and Debugging

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VLSI Physical Design Automation

VLSI Design Cycle

System Specification

Functional Design

Logic Design

x = (AB*CD)+(A+D)+(A(B+C)) Y=(A(B+C)+AC+D+A(BC+D))

Circuit Design

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VLSI Physical Design Automation

VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging

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VLSI Physical Design Automation

Physical Design
Physical design converts a circuit description into a geometric description. This description is used to manufacture a chip. The physical design cycle consists of 1. Partitioning 2. Floorplanning and Placement 3. Routing 4. Compaction
~

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VLSI Physical Design Automation

Physical Design Cycle

Circuit
Design

Physical Design

cutline 2

(a)

Partitioning

cutline 1

(b)

Floorplanning Placement
&

(c)

Routing

(d)

Compaction

Fabrication

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VLSI Physical Design Automation

Design Styles
Complexity of VLSI curcuits

Performance

Size

Cost

Market time

Different design styles

Full custom

Gate array

Standard cell

FPGA

Cost, Flexibility, Cost

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VLSI Physical Design Automation

Full Custom Design Style

Pad Metal 1

Via

Metal 2

Data path PLA I/O

ROM/RAM

Random logic A/D converter

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VLSI Physical Design Automation

Standard Cell Design Style

VDD Metal 1 Cell Metal 2 Feedthrough GND D C C B

Cell library
Cell A Cell B

Cell C

Cell D

Feedthrough cell

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VLSI Physical Design Automation

Gate Array Design Style

A C B

VDD

Metal 1

Metal 2

GND

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VLSI Physical Design Automation

FPGA Design Style

P A D F B P C P
4 1

G E

(a)
P A 0 0 1 1
1

P D 0 1 1 0 B 0 0 1 1

P E 0 1 1 1 D 0 0 1 1

P F 1 1 1 0 D 0 0 1 1

B 0 1 0 1

C 0 1 0 1

E 0 1 0 1

E 0 1 0 1

G 0 0 0 1

(b)
VDD GND

B
F

10

11

12

(c)

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VLSI Physical Design Automation

Comparisons of Design Styles

style full-custom standard cell gate array FPGA cell size variable xed height xed xed cell type variable variable xed programmable cell placement variable in row xed xed interconnections variable variable variable programmable uneven height cells are also used.

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VLSI Physical Design Automation

Comparisons of Design Styles

style full-custom standard cell gate array Area compact compact moderate to moderate Performance high high moderate to moderate Fabrication layers All All routing layers

FPGA large low none

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VLSI Physical Design Automation

History of VLSI CAD

Year 1950-1965 1965-1975 1975-1985 Manual design Design Tools Layout editors Automatic routers (for PCB) E cient partitioning algorithm Automatic placement tools Well de ned phases of design of circuits Signi cant theoretical development in all phases

1985-present Performance driven placement and routing tools Parallel algorithms for physical design Signi cant development in underlying graph theory Combinatorial optimization problems for layout
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VLSI Physical Design Automation

VLSI CAD Conferences

ACM/IEEE Design Automation Conference (DAC) International Conference on Computer Aided Design (ICCAD) IEEE International Symposium on Circuits and Systems (ISCAS) International Conference on Computer Design (ICCD) IEEE Midwest Symposium on Circuits and Systems (MSCAS) IEEE Great Lakes Symposium on VLSI (GLSVLSI) European Design Automation Conference (EDAC) International Conference on VLSI Design

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VLSI Physical Design Automation

VLSI CAD Journals

IEEE Transactions on CAD of Circuits and Systems Integration Transactions on Circuits and Systems Journal of Circuits, Systems and Computers Algorithmica SIAM journal of Discrete and Applied Mathematics IEEE Transactions on Computers

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VLSI Physical Design Automation

Summary
1. Physical design is one of the steps in the VLSI design cycle. 2. Physical design is further divided into partitioning, placement, routing and compaction. 3. There are ve major design styles, e.g., full custom, standard cell, gate array, sea of gates and FPGAs. 4. There are three alternatives for packaging of chips, e.g., PCB, MCM and WSI. 5. Automation reduces cost, increases chip density, reduces timeto-market, and improves performance. 6. CAD tools currently lag behind fabrication technology, which is hindering the progress of IC technology.

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