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Digital Logic Design

Digital Logic Design

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Published by: kabs on Sep 27, 2012
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05/13/2014

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Code No: R059210504
Set No. 1
II B.Tech I Semester Supplimentary Examinations, February 2008DIGITAL LOGIC DESIGN( Common to Computer Science & Engineering, Information Technologyand Computer Science & Systems Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆ ⋆ ⋆ ⋆
1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read frommemory. What was the original 8-bit data word that was written in to memory if 12-bit words read out is as follows? [4
×
4](a) 001111101010(b) 101110010110(c) 101110110100(d) 110011010111.2. (a) Explain in detail, the various levels of integration in ICs.(b) Obtain the Dual of the following Boolean expressions.i. AB + A(B + C) + B’(B + D)ii. A + B + A’B’C.(c) Obtain the complement of the following Boolean expressions. [8+4+4]i. A’B + A’BC’ + A’BCD + A’BC’D’Eii. ABEF + ABE’F’ + A’B’EF.3. (a) Draw the multiple level NOR circuit for the following expression:
A
(
B
+
+
D
) +
BCD
(b) Simplify the following functions and implement two level NOR gates: [8+8]i.
(
A,B,C,D
) = Σ0
,
2
,
4
,
6
,
8
,
9
,
10
,
11
,
12ii.
(
w,x,y,z 
) = Σ5
,
6
,
9
,
114. (a) Implement 64
×
1 multiplexer with four 16
×
1 and one 4
×
1 multiplexer.(Use only block diagram).(b) A combinational logic circuit is defined by the following Boolean functions.
1
=
ABC 
+
AC 
2
=
ABC 
+
AB
3
=
ABC 
+
AB
Design the circuit with a decoder and external gates. [8+8]5. (a) Define the following terms related to flip-flops.i. hold time1 of 2
 
Code No: R059210504
Set No. 1
ii. propagation delayiii. clock andiv. direct inputs.(b) Write an HDL functional description of a D- flip-flop and J-K- flip-flop. [8+8]6. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagramand timing diagrams.(b) Draw the block diagram and explain the operation of serial transfer betweentwo shift registers and draw its timing diagram. [8+8]7. (a) Explain the construction of a basic memory cell and also explain with diagramthe construction of a 4 * 4 RAM(b) Given a 32*8 ROM chip with an enable input, show the external connectionsnecessary to construct a 128 * 8 ROM with four chips and a decoder. [8+8]8. (a) Give the implementation procedure for a SR Latch using NOR gates.(b) An asynchronous sequential circuit is described by the excitation and outputfunctions.Y =
x
1
x
2
+ (
x
1
+
x
2
)yZ = yImplement the circuit defined above with a NOR SR latch. Repeat with aNAND SR latch. [6+10]
⋆ ⋆ ⋆ ⋆
2 of 2
 
Code No: R059210504
Set No. 2
II B.Tech I Semester Supplimentary Examinations, February 2008DIGITAL LOGIC DESIGN( Common to Computer Science & Engineering, Information Technologyand Computer Science & Systems Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆⋆⋆⋆⋆
1. Convert the following to Decimal and then to Octal.(a) 2
A
7
16
(b) 1
BB
16
(c) 10110111
2
(d) 11011010
2
(e) 387
10
(f) 677
10
[3+3+3+3+2+2]2. (a) Simplify the following Boolean functions.i. x”yz + x’yz’ + xy’z’ + xy’zii. x’yz + xy’z’ + xyz + xyz’iii. x’z + x’y + xy’z + yziv. x’y’z’ + x’yz’ + xy’z’ + xy’z + xyz’.(b) Obtain the complement of the following Boolean expressions. [8+8]i. A’C’ + ABC + AC’ii. (x’y’ + z)’ + z + xy + wziii. A’B(D’ + C’D) + B(A +A’CD)iv. (A’ + C)(A’ + C’)(A + B + C’D).3. (a) Obtain minimal SOP expression for the given Boolean expression and hencedraw the circuit using NOR gates.
(
A,B,C,D
) =
BC 
+
ABD
+
A BD
+
ABCD
(b) Draw NOR-logic diagram that implements the following function:
(
A,B,C,D
) = Π0
,
1
,
2
,
3
,
4
,
8
,
9
,
12 [8+8]4. (a) Implement 64
×
1 multiplexer with four 16
×
1 and one 4
×
1 multiplexer.(Use only block diagram).(b) A combinational logic circuit is defined by the following Boolean functions.
1
=
ABC 
+
AC 
2
=
ABC 
+
AB
3
=
ABC 
+
AB
Design the circuit with a decoder and external gates. [8+8]1 of 2

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