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Clock Gating Lab Notes[1]

Clock Gating Lab Notes[1]

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Published by: Rajesh Mangalore Anand on Sep 30, 2012
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ELEC6016 – Clock Gating Laboratory Notes
CLOCK GATING USING SYNOPSYS DESIGN COMPILER
Aims:
1.
 
To understand the principle of clock gating2.
 
To gain experience in using Synopsys Design Compiler to implement clockgating in RTL design3.
 
To demonstrate the benefit of clock gating in reducing power consumption
Procedure:
1.
 
Fig. 1 (a) shows the block diagram of the design used to incorporate clock-gating.The functionality of the design is covered in your lecture notes. The keyfunctionality is:
output only one 16 bit data from an incoming data stream by generating a single-cycle active-high “
enable
” signal generated using a counter and an“enable generator” module.
(Fig. 1(b) shows the functionality, generated usingModelsim).2.
 
Download the zipped RTL files (written in VHDL format) of the blocks (asshown in Fig. 1) from the following link:https://secure.ecs.soton.ac.uk/notes/elec6016/lpd/clock-gating-lab.zipand copy to “/home/[
user
]/clockgating/” ([
user
] is your user name). If the“clockgating” directory does not exist, type “mkdir clockgating” in commandprompt, followed by “cd clockgating” command to change to newly created“clockgating” directory.The following files are included:(a)
 
counter8.vhd
– creates a counter counting from 0 to 7(b)
 
en_gen.vhd
– creates one single-cycle active-high “enable” signal whencounter value reaches 7. (See Fig. 1 (a) and (b)).(c)
 
flop7.vhd
- outputs one 16 bit data from the incoming data-stream whenthe “enable” signal is high.(d)
 
top.vhd
– top design combining above three modules.
Page 1 of 7
 
 
 Fig. 1 (a)Fig. 1(b)ASIC SYNTHESIS USING SYNOPSYS DESIGN COMPILER (DC)PART-A : SYNTHESIZE WITHOUT CLOCK-GATING
1.
 
From your Windows work-station connect to “hind” or “esdcad5” UNIX serverusing NX client (Click “Configure”, enter “hind.ecs.soton.ac.uk” or“esdcad5.ecs.soton.ac.uk” as host) with your user name and password.2.
 
Right-click on UNIX desktop, click on “Open Terminal”.3.
 
In UNIX terminal command prompt type the following:>> source /home/esdcad/scripts/esd_tcshrc>> source /home/esdcad/scripts/synopsys_linux_galaxy_C-2009.06>> source /home/esdcad/scripts/license4.
 
In UNIX command prompt type the following: dc_shell-xg-t
Page 2 of 7
 
 
5.
 
It will take you to the dc_shell now.6.
 
This needs “Technology Library” information from you.dc_shell>>set search_path /
home/esdcad/designkits/st/st12/v92/CORE9GPLL _SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS
dc_shell>> set target_library [list CORE9GPLL_Worst.db]dc_shell>> set link_library [list {*} CORE9GPLL_Worst.db CORE9GPLL_Best.db]dc_shell>> set symbol_library [list CORE9GPLL.sdb]7.
 
Now you need to read your design in DC. You can simply use “read” commandto read your RTL level design (verilog/VHDL).
Note:
In the commands below,
RTL_PATH
is the path where your RTL files aresaved.The commands are shown below:dc_shell>> read_file -format vhdl ./RTL_PATH/counter8.vhddc_shell>> read_file -format vhdl ./RTL_PATH/en_gen.vhddc_shell>> read_file -format vhdl ./RTL_PATH/flop7.vhddc_shell>> read_file -format vhdl ./RTL_PATH/top.vhd(
Note:
you can type the following in the DC command prompt to know which fileformats are supported “>> man read_file”. Currently DC supports VHDL, Verilog,System verilog (sverilog))8.
 
Now you need to link your design with the library specified earlier:dc_shell>> link9.
 
Now you need to apply “design constraints” (clock constraints, multicycle path,false path etc.) within dc_shell.In your dc_shell command window simply source the constraint file (
clock.con
) file asfollows:dc_shell>> source ./RTL_PATH/clock.con(
Note
: You can open
clock.con
file using a text editor (e.g vi, emacs or nedit).10.
 
Now you are ready to do the “compilation” of your whole design under theavailable technology library. Command is as follows:dc_shell>> compile
Note
: does not insert clock gating ckt, so use this command if you do not want clockgating11.
 
Power Analysis:
 You can see “approximate power” consumption by typing the following commandwithin dc_shell:
Page 3 of 7
 

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