Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
0Activity
0 of .
Results for:
No results containing your search query
P. 1
Ambaamba bus

Ambaamba bus

Ratings: (0)|Views: 7 |Likes:
Published by Rupesh Gupta

More info:

Published by: Rupesh Gupta on Oct 25, 2012
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See more
See less

12/04/2012

pdf

text

original

 
 
Building an AMBA AHB compliant Memory Controller
 
Hu Yueli
1,2
, Yang
 
Ben
1,2
 
1.
 
Key Laboratory of Advanced Display and System Applications, Ministry of Education,2.
 
College of Mechanical and Electronic Engineering and Automation,Shanghai University, Shanghai 200072, Chinahuyueli@shu.edu.cn, benny0216@hotmail.com
 Abstract 
- Microprocessor performance has improvedrapidly these years. In contrast, memory latencies andbandwidths have improved little. The result is that thememory access time has been a bottleneck which limits thesystem performance. Memory controller (MC) is designedand built to attacking this problem. The memory controlleris the part of the system that, well, controls the memory.The memory controller is normally integrated intothe system chipset. This paper shows how to build anAdvanced Microcontroller Bus Architecture (AMBA)compliant MC as an Advanced High-performance Bus(AHB) slave. The MC is designed for system memorycontrol with the main memory consisting of SRAM andROM. Additionally, the problems met in the design processare discussed and the solutions are given in the paper.
 Keywords - ARM; AMBA; Memory Controller; AHB bus
I.
 
I
 NTRODUCTION
 
With the improvement of Microprocessor these years,the memory access time has been a bottleneck whichlimits the system performance. Memory controller (MC)is designed and built to attacking this problem. Thememory controller is the part of the system that, well,controls the memory. It generates the necessary signals tocontrol the reading and writing of information from andto the memory, and interfaces the memory with the other major parts of the system. The memory controller isnormally integrated into the system chipset. In this paper,an Advanced Microcontroller Bus Architecture (AMBA)compliant memory controller is designed for systemmemory control with the main memory consisting of SRAM and ROM. The memory controller is compatiblewith Advanced High-performance Bus (AHB) which is anew generation of AMBA bus, so we call it “AHB-MC”.The AHB-MC has several features which are shownas flows:
¾
 
Designed with synthesizable HDL for ApplicationSpecific Integrated Circuit (ASIC) synthesis
¾
 
Supports multiple memory devices including staticrandom access memory (SRAM), read-onlymemory (ROM)
¾
 
Complies with AMBA AHB protocol
¾
 
Supports one to four memory banks for SRAM andROM
¾
 
Programmable memory timing register andconfiguration registers
¾
 
Shared data path between memory devices to reduce pin count
¾
 
Asynchronous FIFO to support burst transaction up to16-beatsThis paper describes how to build the AHB-MC. Andcombining the problem met in the process of designing,the corresponding solutions are presented. Finally, thesimulation results are presented.II.
 
A
RCHITECTURE OF
AHB-MCThe AHB-MC mainly consists of three modules:AHB slave interface, configuration interface, and externalmemory interface[1]. Figure 1 shows the architecture of AHB-MC.
AHB SlaveInterfaceExternalMemoryInterfaceReadDataFIFOReadDataFIFO
 
WriteDataFIFOCmdFIFOInternalSRAMControlLogicROMExternalSRAMAMBA AHBHCLKMCLControlLogicAHB toAPB bridgeConfigrationRegisters
ConfigurationInterface
 
Figure 1.
 
Architecture of AHB-MC
 A.
 
 AHB slave interface
The AHB slave interface converts the incoming AHBtransfers to the protocol used internally by the AHB-MC.The state machine is shown in Figure 2.
IDLERD_SEQRD_ROM_WAITresetWR_RAM_WAITRD_RAM_WAITCMD_GENWR_SEQstartrd_romrd_ramwr_ram!seqwrWait=0ramWait=0romWait=0!seqseqseq
 
Figure 2.
 
AHB slave interface state machine
2011 Third International Conference on Measuring Technology and Mechatronics Automation
978-0-7695-4296-6/11 $26.00 © 2011 IEEEDOI 10.1109/ICMTMA.2011.167658
 
 
 B.
 
 External memory interface
The external memory issues commands to thememory from the command FIFO, and controls the cycletimings of these commands. The state machine is shownin Figure3.
Figure 3.
 
External memory interface state machine
Figure 4 and Figure 5 show the timing of a read frommemory and a write to memory with two wait states[2].
Figure 4.
 
Memory read with two wait statesFigure 5.
 
Memory write with two wait states
1)
 
Memory bank select 
Because system will change the memory map after system boot, AHB-MC is designed to support a remapsignal which is used to provide a different memory map.AHB-MC has four memory banks, which are selected byXCSN signal. The XCSN signal is controlled by theaddress of a valid transfer, and the system memory mapmode. So before the system memory is remapped, the boot ROM at 0x3000 0000 is also mapped to the baseaddress of 0x0000 0000 as shown in Table 1.
Table 1.
 
XCSN coding
InputInputInput OutputHSelectRemapHADDR[29:28] XCSN
0XXX 11111000 01111001 11011010 10111011 01111100 11101101 11011110 10111111 0111
2)
 
Memory write control 
To support for writing in word (32-bits), half-word(16-bits) and byte (8-bits), the XWEN signal is used inthe AHB-MC. Table 2 shows the relationship betweenXCSN and the inputs from AHB bus.
Table 2.
 
XWEN coding
HSIZE[1:0] HADDR[1:0] XWEN[3:0]
10 (word)XX000001(half)0X110001(half)1X001100(byte)00111000(byte)01110100(byte)10101100(byte)110111
C.
 
Configuration interface
The main function of the configuration interface is tochange the configuration registers (SETCYCLE andSETOPMODE register) according to the commands fromAHB to APB bridge which converts AHB transfers fromthe configuration port to the APB transfers that theconfiguration interface require[3]. Each memory chipsupported by AHB-MC has two registers (CYCLEregister and OPMODE register), which contain all thetiming parameters that are required for the controller toset correct access timings. Which cycle and operationmode registers are updated is determined by theconfiguration registers: SETCYCLE and SETOPMODEas shown in Figure 6.
 
659
 
 
Figure 6.
 
Chip configuration register 
III.
 
B
URST TRANSFER SUPPORT
 With the increasing system frequency, it’s hard toaccomplish the address decoding and memory accessoperations in one clock cycle. Therefore, wait states areinserted into the data cycle to ensure there is enough timefor address decoding and memory accessing. But themethod that inserting wait state will cause system performance drop dramatically.Therefore, a sequential-access (burst) method is presented to resolve this problem in this paper. In thismethod, all AHB fixed length burst types are directlytranslated to fixed length bursts, and all undefined lengthINCR bursts are converted to INCR4 bursts. Burstoperation has performance benefits because when the first beat of a burst is accepted, it contains data about theremaining beats. For example, when AHB-MC got thefirst beat of a read burst, all the data required to completethe transfer can be read from memory and restored in theread data FIFO. SO this first transfer has some delay before data is returned. But subsequent beats of the burstcan have less delay because the data they require mighthave already been prepared in the FIFO.To further improve the system performance, aRETRY response is used that AHB-MC can release the bus when it is preparing the data[4]. This mechanismallows the transfer to finish on the bus and thereforeallows a higher-priority master to get access to the bus.The state machine is showed in Figure 7.IV.
 
M
EMORY SYSTEM
 In the arm architecture, instructions are all 32-bits,while instructions are 8-bits in the external ROM andSRAM. Therefore the lowest two addresses of ROM andSRAM are not connected to the external address bus.Additionally, to support byte writing, SRAM needs to beseparated as four independent banks or has a byte-writeenable signal. The basic memory system architecture isshown in Figure 8.
MCSRAMSRAMSRAMSRAMROMROMROMROMD[7:0]D[7:0]D[7:0]D[7:0]D[7:0]D[7:0]D[7:0]D[7:0]XA[m+2:2]XD[23:16]XD[15:8]XD[7:0]XA[m+2:2]XA[m+2:2]XA[m+2:2]XA[n+2:2]XA[n+2:2]XA[30:0]XD[31:0]XD[31:24]XA[n+2:2]XA[n+2:2]SRAM Control SignalsROM Control Signals
 
Figure 8.
 
Memory system architecture
V.
 
A
SYNCHRONOUS CLOCK 
 The AHB-MC has two clock domains: AHB clock domain and external memory clock domain as shown inFigure 9. Asynchronous FIFO is used between two clock domains as a data buffer.
AHB SlaveInterfaceExternalMemoryInterfaceReadDataFIFOReadDataFIFO
 
WriteDataFIFOCmdFIFOInternalSRAMControlLogicROMExternalSRAMAMBA AHBControlLogicAHB toAPB bridgeConfigrationRegistersConfigurationInterfaceExternal memory clock domainAHB clock domain
 
Figure 9.
 
Clock domains
The main benefit of asynchronous clocking is that youcan maximize the system performance, while running thememory interface at a fixed system frequency.Additionally, in sleep-mode situations when the system isnot required to do much work, you can lower thefrequency to reduce power consumption[5].However, asynchronous clock will cause the flip-flopgoing metastable state and not converging to a legalstable state by the time the output must be sampled againas shown in Figure 10.To resolve this problem, the most common way isinserting a two-flip-flop synchronizer as shown in Figure11.
Figure 7.
 
Sequential-access state machine
660

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->