Pamantasan ng Lungsod ng Maynila (University of the City of Manila) Intramuros, Manila College of Engineering and Technology Computer Studies

Department

Computer Organization, Architecture and Machine Level Programming SAP-1 MODIFICATION

Submitted by: Aromin, Denisse Aubrey L. Buraga, Vincent Paul B. Dianzen, Fruzzel Paul P. Francia, Munich J. Garillo, Lois Eunice R. Jimenez, Mary Grace S. Tolentino, Joshua Nico V.

Submitted to: Prof. Melannie Mendoza March 11, 2011

INTRODUCTION
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Malvino. The SAP-1 design contains the basic necessities of a functional microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set SAP-1 is very limited and simple. Its main purpose is to introduce all the crucial ideas behind computer operation without burying in unnecessary details. But even simple computer like SAP covers many advanced concepts. SAP-1 is the evolution toward modern computers. Be ready to SAP-1 and you will be ready to SAP-2.

The features of SAP-1 computer are:

RAM Instruction Registers Program counter Memory Address Register (MAR) Arithmetic Logic Unit Controller-Sequencer Accumulator B Register Output Register Binary Display with: AND Accumulator OR Accumulator Exclusive OR Accumulator Rotate Accumulator Left Rotate Accumulator Right
The instruction format of SAP-1 Computer is:
(XXXX) (XXXX)

The first four bits make the opcode while the last four bits make the operand (address).

INSTRUCTION SET CONSISTS OF FOLLOWING INSTRUCTIONS:

Mnemonic LDA ADD SUB OUT HLT ANA ORA XRA RAL RAR Load addressed accumulator.

OPERATION memory contents

OPCODE into 0000

Add addressed memory contents to accumulator. 0001 Subtract addressed memory contents from accumulator. Load accumulator data into output register. Stop processing. AND Accumulator register. OR Accumulator register. contents contents with with 0010 1110 1111 designated 1010 designated 0101 0100 1000 1001

Exclusive OR accumulator. Rotate Accumulator Left. Rotate Accumulator Right.

MACHINE CYCLE AND INSTRUCTION CYCLE

SAP1 has six T-states (three fetch and three execute cycles) that are reserved for each instruction. Not all instructions require all the six T-states for execution. The unused T- state is marked as No Operation (NOP) cycle. Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at every falling edge of clock pulse. The ring counter output is reset after the 6th Tstate. FETCH CYCLE T1, T2, T3 machine cycle EXECUTE CYCLE T4, T5, T6 machine cycle

ARCHITECTURE
1. Program Counter (PC) Implemented in pc.v file. It is part of the control unit and counts from 0000 to 1111 and it signals the memory address of next instruction to be fetched and executed. It is reset to 0000 before each computer run. When the computer runs, the program counter sends address to 0000 to the memory and it is incremented to get 0001. 2. Input and MAR (MAR) Implemented in inputMAR.v file Below the program counter is the input and MAR block. It includes the address and data switch registers. The MAR is part of the SAP-1 memory. During a computer run, the address in PC is latched into Memory Address Register (MAR). 3. RAM Implemented in mem16k.v file. The RAM is a 16 x 8 static TTL. The program code to be executed and data for SAP1 computer is stored here. During a computer run, the RAM receives 4-bit addresses from MAR and a read operation is performed. Hence, the instruction or data word stored in RAM is placed on the W bus for use by some other part of the computer. It is asynchronous RAM, which means that the output data is available as soon as valid address and control signal are applied.

4. Instruction Register (IR) Implemented in ir.v file It is part of the control unit. To fetch an instruction from the memory the computer does a memory read operation. This places the memory

address contents in the W bus. IR contains the instruction (composed of OPCODE+ADDRESS) to be executed by SAP1 computer. 5. Controller- Sequencer Implemented in cu.v file. This resets the program counter to 0000 and wipes out the last instruction in the instruction register. It generates the control signals for each block so that actions occur in desired sequence. CLK signal is used to synchronize the overall operation of the SAP1 computer. A 12 bit word comes out of the Controller-Sequencer block. This control word determines how the registers will react to the next positive CLK edge. The 12 wires carrying the control word are called the control bus. 6. Accumulator

Implemented in accumulator.v file. It is a 8 bit buffer register that stores intermediate results during a
computer run and has two outputs. The two-state output goes to the W bus. Therefore the 8 bit accumulator word continuously drives the adder- subtracter. The same word appears on the W bus when Ea is high.

It is always one of the operands of ADD, SUB and OUT instructions.

7. Adder-Subtracter

Implemented in addersubtracter.v file.

It is a 2's complement adder-subtractor.

This module is asynchronous (unclocked), which means that its
contents can change as soon as the input words change.

When Su is low, the sum out of the adder-subtracter is S = A + B. When Su is high the difference appears: A = A+B

8. B Register

Implemented in register.v file. It is 8 bit buffer register which is primarily used to hold the other
operand (one operand

is always accumulator) of mathematical operations. The two-state output of the B register drives the adder-subtracter, supplying the number to be added or subtracted from the contents of the accumulator. 9. Output Register

This registers hold the output of OUT instruction.

Often called an output port because processed data can leave the computer through this register. 10. Binary Display

It is a row of eight Light Emitting Diodes to show the contents of

output register.
The LED connects to one flip-flop of the output port, the binary display

shows us the contents of the output port.

INSTRUCTION SET
Programming a computer means loading the instructions step-by-step into the memory before the start of the computer run. Before you can program a computer , you must learn its instruction set.

LDA
It stands for load the accumulator. A complete LDA instruction includes the hexadecimal address of the data to be loaded.

ADD
ADD is another SAP-1 instruction. A complete ADD instruction includes the address of the word to be added. The addressed RAM word goes to the B Register and the addersubtracter output to the accumulator.

SUB
A complete SUB instruction includes the address of the word to be subtracted. The addressed RAM word goes to the B Register and the adder-subtracter output to the accumulator.

OUT
The instruction OUT tells the SAP-1 computer to transfer the accumulator contents to the output port. After OUT has been executed, we can see the answer to the problem being solved.

HLT
HLT stands for HALT. This instruction tells the computer to stop processing data. HLT marks the end of a program, similar to the way a period marks the end of a sentence. HLT is complete by itself.

ANA
ANA means to AND the accumulator contents with the designated register. The result is stored in the accumulator. Two ANA instructions are available in SAP-2: ANA B ad ANA C.

ORA
ORA is the mnemonic for OR the accumulator with the designated register. The two ORA instructions in SAP-2 are ORA B and ORA C.

XRA

XRA means xor the accumulator with the designated register. The SAP-2 instruction set contains XRA B and XRA C.

RAL
RAL is the mnemonic for rotate the accumulator left. This instruction will shift all bits to the left and move the MSB into the LSB position.

RAR
RAR stands for rotate the accumulator right. The bits shift to the right, the LSB going to the MSB position.

FETCH AND EXECUTE CYCLE

SAP 1 ARCHITECTURE
W BUS

CP CLK CLR

LA
8 8

EP

PROGRAM COUNTER

4 8

ACCUMULATOR

CLK EA

LM CLK
Input AND MAR
4 8

ADDER/ SUBTRACTOR/ANA/ ORA/RAR/RAL/XRA/ XNA

SU EU

CE LI CLK CLR EI

16x8 RAM

8 8

LB
B REGISTER

CLK

INSTRUCTION REGISTER
4 4

8 8

LO
OUTPUT REGISTER

CLK

CONTROLLER SEQUENCER
12

CLK CLK CLR CLR

BINARY DISPLAY

CP EP LM CE LI EI LA EA

SU EU LB LO

CONCLUSION
We became familiar with the working of a 8-bit microprocessor and the way each module contributes to the overall functioning of the computer. Although the concept of SAP1 is very simple, the knowledge gained while designing it can be extended to design of more complex microprocessors.

REFERENCE
Albert Paul Malvino. Digital Computer Electronics An Introduction to Microcomputers: SAP-1(Page 140). Tata McGraw-Hill Publishing Company Limited 1990.