AHDL

1.

1.1

AHDL (

Altera)
,

Assign Assignment & Configuration File (.acf)

MAX+PLUS II.

.


.

, ,

(Message Processor )

MAX+PLUS

II

(AHDL Text Design Files (. tdf)).

TDF

1.2

MAX+PLUS

II

(AHDL Text Design Export Files (.tdx))

(Text Design Output Files (. tdo)),

TDF

AHDL

AHDL

,
.

AHDL

TDF
.

TDF ,
MAX+PLUS II

, ,
AHDL .
AHDL
.

,
TDF

(Graphic Design File (. gdf)).

300

AHDL
.
1.2.1

AHDL

AHDL . AHDL -

AHDL?

(LPM),

AHDL,

AHDL

1.

Template

AHDL

Template.

2.

Template

Section.
3.

OK.

TDF ,

.
AHDL ,

(_

_)

TDF .

1.2.2

chip_enable

Files

(.tdo)),

AHDL

, .

(Assignment & Configuration Output Files (.aco)).

TDO

(address[15..0]

==

END;

(Text Design
Output

H"0370");

15 0
.

H"0370"

.
1.2.4

AHDL

File: Project Name Project Set Project

to Current File

ACO

Assignment & Configuration File

).

. ,

TDO

. ,

TDO

130.

1. Generate AHDL TDO File

2. Start

Constant ,

File: Project Save & Compile

Define .

Simulate

Project

AHDL

decode2.tdf,

decode1.tdf,

, 370 Hex.
SUBDESIGN decode1
(
address[15..0] : INPUT;
chip_enable
)
BEGIN

: OUTPUT;

IO_ADDRESS

H"0370".
CONSTANT IO_ADDRESS = H"0370";
SUBDESIGN decode2
(
a[15..0] : INPUT;

decode1.tdf,

. AHDL

USED, CEIL, FLOOR.

MAX+PLUS II.

1.2.3

: ,
. AHDL

Processing.

&

, ,

TDO :

Compile

UPPER_LIMIT ,

Save,

ce

: OUTPUT;

)
BEGIN
ce = (a[15..0] == IO_ADDRESS);
END;

.
.

strcmp.tdf,

1.2.5

FAMILY
Assert

FLEX 8000.

AHDL
, ,
.

PARAMETERS

DEVICE_FAMILY
%

DEVICE_FAMILY

1.2.5.1

);

CONSTANT FAMILY = "FLEX8000";

SUBDESIGN strcmp

a : INPUT;

b : OUTPUT;

BEGIN

boole1.tdf,

IF (DEVICE_FAMILY == FAMILY) GENERATE

ASSERT

.
SUBDESIGN boole1

REPORT "

FLEX8000 "

a0, a1, b : INPUT;

SEVERITY INFO;

out1, out2 : OUTPUT;

b = a;

ELSE GENERATE

BEGIN

ASSERT

out1 = a1 & !a0;

REPORT "

% "

out2 = out1 # b;
END;

DEVICE_FAMILY
SEVERITY ERROR;

b = a;
END GENERATE;

out1

out2 out1 b.

END;

1 0,
.

minport.tdf,

MAX,

1.2.5.2

Subdesign.

PARAMETERS (WIDTH);

DEFINE MAX(a,b) = (a > b) ? a : b;

SUBDESIGN minport

boole3.tdf,

boole1.tdf,

dataA[MAX(WIDTH,0)..0] : INPUT;

dataB[MAX(WIDTH,0)..0] : OUTPUT;

32 .

)
BEGIN
dataB[] = dataA[];
END;

SUBDESIGN boole3
(
a0, a1, b : INPUT;
out1, out2 : OUTPUT;

BEGIN

out1 = a1 tiger:& !a0;

out2 = out1 panther:# b;

, .

END;

, ,

boole3.rpt boole1.rpt

. ,
tiger~0. ,

-- boole3.rpt equations:

-- Node name is 'out1' from file "boole3.tdf" line 7,

col 2

ID

-- Equation name is 'out1', location is LC3_A1, type is

1.2.5.3

output
out1 = tiger~0;

,
-- Node name is 'tiger~0' from file "boole3.tdf" line

7, column 18
-- Equation name is 'tiger~0', location is LC2_A1,

Node

Variable ,

.
,

type is buried

tiger~0 = LCELL( _EQ002);

_EQ002 = !a0 & a1;

, .

-- boole1.rpt equations:
-- Node name is 'out1' from file "boole1.tdf" line 7,

boole2.tdf,

boole1.tdf, .

col 2
-- Equation name is 'out1', location is LC3_A1, type is

SUBDESIGN boole2

output

out1 = _LC2_A1;

a0, a1, b
out

-- Node name is ':33' from file "boole1.tdf" line 7, col

: INPUT;
: OUTPUT;

12

-- Equation name is '_LC2_A1', type is buried

VARIABLE
a_equals_2 : NODE;
BEGIN

LC2_A1 = LCELL( _EQ001);

a_equals_2 = a1 & !a0;

_EQ001 = !a0 & a1;

out = a_equals_2 # b;

END;

a_equals_2

, ,

boole3.rpt

, tiger~0,

boole1.tdf

a1

&

!a0.

,
.

ID :33
.

(NODE),

(TRI_ STATE_ NODE).

NODE

TRI_STATE_NODE

,
.

NODE

Options

- - .

, Defaults ,

d[] == 1. use_exp_in[]

VCC

- ,

GND

- .

TRI_STATE_NODE

MSB,

a[].

00,

a[]

TRI_STATE_NODE,

use_exp_out[]

NODE.

1.2.5.4

256

( ),

, VCC, GND, 1 0.

Options

, ,

1,

VCC GND,

VCC.

GND.

. ,

: (MSB)
(LSB) - .

a[4..1] = b[2..1] .

, [ ]

. , a[4..1]

a[]; b[5..4][3..2] b[][].

group1.tdf,

a4 = b2
a3 = b1
a2 = b2
a1 = b1

OPTIONS BIT0 = MSB;

CONSTANT MAX_WIDTH = 1+2+3-3-1;
% MAX_WIDTH = 2 %

1.2.5.5

SUBDESIGN group1

a[1..2], use_exp_in[1+2-2..MAX_WIDTH] : INPUT;

d[1..2],use_exp_out[1+2*2-4..MAX_WIDTH]
OUTPUT;

If

Then

If Then

Case

dual_range[5..4][3..2] : OUTPUT;

. Case

BEGIN

d[] = a[] + B"10";

use_exp_out[] = use_exp_in[];

dual_range[][] = VCC;
END;

 ,
If Then Case ,
,

Generate .

)
BEGIN

If

CASE code[] IS

WHEN 0 => out[] = B"0001";

WHEN 1 => out[] = B"0010";

WHEN 2 => out[] = B"0100";

1.2.5.5.1

If Then

WHEN 3 => out[] = B"1000";

priority.tdf,

END;

0, 1, 2 3. Case
=> .

SUBDESIGN priority

, code[] 1, out1

(
low, middle, high

END CASE;

: INPUT;

highest_level[1..0] : OUTPUT;

B"0010".

WHEN

)
BEGIN

If Then

1.2.5.5.3

IF high THEN

Case

highest_level[] = 3;
ELSIF middle THEN

If Then

highest_level[] = 2;

Case .

ELSIF low THEN

highest_level[] = 1;

ELSE

highest_level[] = 0;

END IF;
END;

If

Then

.
high, middle, low

, IF ELSIF

. Case,

VCC.

If

Then

IF ELSE , high

, highest_level[] 3.

WHEN

ELSIF

If Then

IF ELSIF (

).

ELSIF

ELSE.

1.2.5.5.2

If

2 4 .

IF/ELSIF

Case
decoder.tdf,

Then .

2- .
If Then

SUBDESIGN decoder
(
code[1..0]
out[3..0]

: INPUT;
: OUTPUT;

IF a THEN
c = d;

IF a THEN
c = d;

END IF;

decode3.tdf,

ELSIF b THEN

16-

IF !a & b THEN

c = e;

c = e;
END IF;

SUBDESIGN decode3
(

ELSE
c = f;
END IF;

IF !a & !b THEN

addr[15..0], m/io

c = f;

rom, ram, print, sp[2..1] : OUTPUT;

: INPUT;

END IF;

)
BEGIN
TABLE

1.2.5.6

m/io, addr[15..0]
print,

AHDL

1,

Truth Table
lpm_compare lpm_decode .
7segment.tdf,

(LED). LED
.

ram,

=> 1,

0,

=> 0,

1,

B"00";

B"100XXXXXXXXXXXXX"
0,

0,

rom,

sp[];

B"00XXXXXXXXXXXXXX"
0,

1,

=>

B"00";

B"0000001010101110"

=> 0, 0,

1,

=> 0, 0,

0,

=> 0, 0,

0,

B"00";
0,

B"0000001011011110"
B"01";

SUBDESIGN 7segment

0,

B"0000001101110000"
B"10";

i[3..0]

: INPUT;

a, b, c, d, e, f, g : OUTPUT;

END TABLE;

END;

BEGIN
TABLE

i[3..0] => a, b, c, d, e, f, g;

Truth Table .

H"0"

=> 1, 1, 1, 1, 1, 1, 0;

H"1"

=> 0, 1, 1, 0, 0, 0, 0;

H"2"

=> 1, 1, 0, 1, 1, 0, 1;

H"3"

=> 1, 1, 1, 1, 0, 0, 1;

TABLE

H"4"

=> 0, 1, 1, 0, 0, 1, 1;

16,384

H"5"

=> 1, 0, 1, 1, 0, 1, 1;

H"6"

=> 1, 0, 1, 1, 1, 1, 1;

H"7"

=> 1, 1, 1, 0, 0, 0, 0;

H"8"

=> 1, 1, 1, 1, 1, 1, 1;

H"9"

=> 1, 1, 1, 1, 0, 1, 1;

H"A"

=> 1, 1, 1, 0, 1, 1, 1;

H"B"

=> 0, 0, 1, 1, 1, 1, 1;

H"C"

=> 1, 0, 0, 1, 1, 1, 0;

AHDL

H"D"

=> 0, 1, 1, 1, 1, 0, 1;

H"E"

=> 1, 0, 0, 1, 1, 1, 1;

H"F"

=> 1, 0, 0, 0, 1, 1, 1;

END TABLE;

rom

addr[15..0],

00.

decode4.tdf,

lpm_decode

END;

decode1.tdf.

16

i[3..0]

INCLUDE "lpm_decode.inc";

Truth Table
SUBDESIGN decode4

B"0010" => B"01100011"; % "c" %

address[15..0]
chip_enable

: INPUT;

B"0001" => B"01100100"; % "d" %

: OUTPUT;

END TABLE;

END;

BEGIN
chip_enable

lpm_decode(.data[]=address[])
WITH

(LPM_WIDTH=16,

Truth

Table ,

LPM_DECODES=2^10)

RETURNS (.eq[H"0370"]);

B"00111111".

END;

1.2.5.7

SUBDESIGN default2
(
a, b, c

. AHDL

select_a, select_b, select_c : INPUT;

BEGIN

wire_or = GND;

GND.

wire_and = VCC;

Defaults

: OUTPUT;

DEFAULTS

: INPUT;

wire_or, wire_and

AHDL.

default2.tdf,

, -

END DEFAULTS;

Truth Table , If Then ,

IF select_a THEN

Case .

wire_or = a;

wire_and = a;
END IF;

,
Subdesign .

IF select_b THEN

default1.tdf,

wire_or = b;

ASCII

wire_and = b;

, .

END IF;

SUBDESIGN default1

IF select_c THEN

wire_or = c;
i[3..0]

: INPUT;

wire_and = c;

ascii_code[7..0] : OUTPUT;

END IF;

END;

BEGIN
DEFAULTS

ascii_code[] = B"00111111"; % ASCII

"?" %

wire_or

a, b, c,
select_a, select_b, select_c.

END DEFAULTS;

VCC, wire_or
GND.

TABLE
i[3..0]

select_a,
=> ascii_code[];

select_b, select_c

B"1000" => B"01100001"; % "a" %

wire_or

B"0100" => B"01100010"; % "b" %

VCC,

wire_and

, ,

"select"

VCC,

VCC

VCC.
1.2.5.8

END IF;
END;

. Altera ,

If

Then

GND.

,
daisy.tdf,

GND.

1.2.5.9

,
MAX+PLUS II

If Then .

. .

"n" (/).

, .

TRI

SUBDESIGN daisy

.
: OUTPUT;

/request_in

: INPUT; %

: INPUT;

/local_grant

BIDIR,

TRI.

/local_request

I/O

bus_reg2.tdf
,

bus_reg3.tdf,

,
.

%
/request_out

: OUTPUT; %

DFF TRI

%
/grant_in

: INPUT; %

%
/grant_out

: OUTPUT;%

.
Register

Instance ,

, Variable .

%
)

SUBDESIGN bus_reg2

BEGIN

bus_reg3
DEFAULTS

SUBDESIGN

/local_grant = VCC;% %

clk : INPUT;

clk : INPUT;

/request_out=VCC;

oe : INPUT;

oe : INPUT;

% %

io : BIDIR;

io : BIDIR;

/grant_out = VCC;

% VCC %

END DEFAULTS;

VARIABLE

IF /request_in == GND # /local_request ==

dff_out : NODE;

GND THEN

VARIABLE
my_dff : DFF;
my_tri : TRI;

/request_out = GND;

BEGIN

BEGIN

END IF;
IF /grant_in == GND THEN

dff_out = DFF(io, clk, ,);

my_dff.d = io;

io = TRI(dff_out, oe);

my_dff.clk = clk;

IF /local_request == GND THEN

/local_grant = GND;
ELSIF /request_in == GND THEN

my_tri.in = my_dff.q;
END;

my_tri.oe = oe;
io = my_tri.out;

/grant_out = GND;
END IF;

END;

out1
io,

: OUTPUT;

TRI, d
D (DFF).

VARIABLE
tnode : TRI_STATE_NODE;

BEGIN

TDF

tnode = TRI(in1, oe1);

tnode = TRI(in2, oe2);

tnode = TRI(in3, oe3);

out1 = tnode;

. Function
TDF

END;

RETURNS .

bidir1.tdf,

tnode,

bus_reg2,

TRI_STATE_NODE, NODE: NODE

FUNCTION bus_reg2 (clk, oe)

RETURNS (io);

TRI_STATE_NODE

SUBDESIGN bidir1

TRI_STATE_NODE,

clk, oe : INPUT;

NODE.

io[3..0] : BIDIR;
1.2.6

)
BEGIN

AHDL

io0 = bus_reg2(clk, oe);

io1 = bus_reg2(clk, oe);

io2 = bus_reg2(clk, oe);

io3 = bus_reg2(clk, oe);

END;

(LPM).

1.2.5.10

OUTPUT

TRI ,

BIDIR,

(Output

1.2.6.1

Enable),

Clock.

Register

Variable .

TRI OUTPUT

BIDIR TRI_STATE_NODE

LPM .

Logic ).

AHDL

,
TDF

tri_bus.tdf,

,
TRI_STATE_NODE

Node.

:
< >.< >

bur_reg.tdf,

Register

SUBDESIGN tri_bus

d Clock,
in[3..1], oe[3..1] : INPUT;

10

SUBDESIGN bur_reg
1.2.6.2

(
clk, load, d[7..0] : INPUT;
q[7..0]

: OUTPUT;

TDF

VARIABLE

Variable. reg_out.tdf,

ff[7..0]

: DFFE;

bur_reg.tdf,

BEGIN
ff[].clk = clk;
ff[].ena = load;

SUBDESIGN reg_out

ff[].d = d[];

(
clk, load, d[7..0] : INPUT;

q[] = ff[].q;

q[7..0]

END;

: OUTPUT;

)
Variable

DFFE(D

clk

).

Logic

Clock

VARIABLE
q[7..0] : DFFE; %
%
BEGIN
q[].clk = clk;

ff[7..0].

q[].ena = load;

q[] = d[];

d[7..0]

END;

ff[7..0].

T, JK, SR

Logic ,

Variable ,

Clock.

Logic .

Clock, Altera
DFFE,

GLOBAL

TFFE, JKFFE, SRFFE

Signal

lpm_reg.tdf,

lpm_dff,

, bur_reg.tdf.

Options ,

Logic .

< >.clk

Logic Options (

Clock,

Global

Individual

Logic

Assign),

Automatic Global Clock

Global

Project

Logic

Synthesis (

Assign).
, , DFFE

INCLUDE "lpm_dff.inc";

SUBDESIGN lpm_reg

q
clk, load, d[7..0] : INPUT;
q[7..0]

Variable ,

q.

: OUTPUT;

)
BEGIN
q[] = lpm_dff (.clock=clk, .enable=load, .data[]=d[])
WITH (LPM_WIDTH=8)
RETURNS (.q[]);
END;

11

 TDF

clk, load, ena, clr, d[15..0] : INPUT;

q[15..0]

probe logic

VARIABLE

Fast

I/O).

: OUTPUT;

my_cntr: lpm_counter WITH (LPM_WIDTH=16);

BEGIN

my_cntr.clock = clk;

my_cntr.aload = load;
my_cntr.cnt_en = ena;

1.2.6.3

my_cntr.aclr

= clr;

my_cntr.data[] = d[];
D
(DFF DFFE) If Then

q[] = my_cntr.q[];
END;

lpm_counter.

ahdlcnt.tdf,

16-

1.2.7

, .

AHDL

SUBDESIGN ahdlcnt

(
clk, load, ena, clr, d[15..0] : INPUT;
q[15..0]

: OUTPUT;

MAX+PLUS II .

VARIABLE
count[15..0]

: DFF;

BEGIN

count[].clk = clk;

count[].clrn = !clr;

IF load THEN

count[].d = d[];

ELSIF ena THEN

count[].d = count[].q + 1;

ELSE

, T D
(TFF DFF)

count[].d = count[].q;

END IF;
q[] = count[];

END;

16

count15.

If Then

count0

Clock.

lpm_cnt.tdf,

lpm_counter
, ahdlcnt.tdf.
INCLUDE "lpm_counter.inc";
SUBDESIGN lpm_cnt

Variable

AHDL,

TDF :

( Variable )

( Logic )

Table Case ( Logic )

12

TDF

Subdesign .

Case

Table . , simple.tdf
1.2.7.1

WHEN
Case .

Variable.

simple.tdf,

(DFF).

If
Then

Case .

WHEN.

Case

simple.tdf

GND, ss
s0 VCC,
s1.

SUBDESIGN simple

clk, reset, d : INPUT;
q

1.2.7.3

: OUTPUT;

1.2.7.2

VARIABLE

Enable

Clock,

Reset

&

ss: MACHINE WITH STATES (s0, s1);

BEGIN

Clock,

Reset,

Clock

Enable

ss.clk = clk;

ss.reset = reset;

CASE ss IS

Logic .

WHEN s0 =>

Clock

q = GND;

simple.tdf,

clk.

IF d THEN

Reset

reset,

ss = s1;

END IF;

ena

Subdesign

ss.ena = ena Logic

WHEN s1 =>

Clock Enable.

q = VCC;
IF !d THEN

SUBDESIGN simple

ss = s0;

END IF;

clk, reset, ena, d : INPUT;

END CASE;

END;

: OUTPUT;

)
VARIABLE

simple.tdf

ss: MACHINE WITH STATES (s0, s1);

ss Variable .
s0 s1,
.

BEGIN
ss.clk = clk;
ss.reset = reset;
ss.ena = ena;
CASE ss IS
WHEN s0 =>
q = GND;

13

(
IF d THEN
ss = s1;

clk, reset

: INPUT;

ccw, cw

: INPUT;

END IF;
WHEN s1 =>

phase[3..0] : OUTPUT;

q = VCC;

)
VARIABLE

IF !d THEN

ss: MACHINE OF BITS (phase[3..0])

ss = s0;

WITH STATES (

END IF;

s0 = B"0001",

END CASE;

s1 = B"0010",

END;

s2 = B"0100",
s3 = B"1000");
BEGIN

1.2.7.3

ss.clk

= clk;

ss.reset = reset;

II

TABLE

MAX+PLUS

ccw,

cw

=>

ss;

s0,

1,

=>

s3;

s0,

x,

=>

s1;

s1,

1,

=>

s0;

s1,

x,

=>

s2;

s2,

1,

=>

s1;

s2,

x,

=>

s3;

s3,

1,

=>

s2;

s3,

x,

=>

s0;

END TABLE;

ss,

END;

phase[3..0],

, ,

. , ccw

Machine

Encoding

One-Hot

Subdesign ,

ss

cw

1 . AHDL ,

Global Project Logic Synthesis

Assign)

.
(

State

),

1.2.7.4

FLEX 6000, FLEX 8000,

FLEX 10K, ,

. ,

WITH

STATES .

moore1.tdf,

stepper.tdf,

,
SUBDESIGN moore1
(

SUBDESIGN stepper

clk

: INPUT;

14

reset : INPUT;

: INPUT;

: OUTPUT;

. moore2.tdf, ,

VARIABLE

ss: MACHINE OF BITS (z)

WITH STATES (s0

0,

s1

1,

SUBDESIGN moore2

s2

1,

s3

0);

clk

BEGIN

: INPUT;

reset : INPUT;

ss.clk

= clk;

ss.reset = reset;

: INPUT;

: OUTPUT;

)
TABLE

VARIABLE

ss: MACHINE WITH STATES (s0, s1, s2, s3);

zd: NODE;

ss,

=>

ss;

BEGIN

s0,

=>

s0;

ss.reset = reset;

s0,

=>

s2;

z = DFF(zd, clk, VCC, VCC);

s1,

=>

s0;

TABLE

s1,

=>

s2;

s2,

=>

s2;

s2,

=>

s3;

s3,

=>

s3;

s0,

s3,

=>

s1;

ss.clk

zd;

=>

s0,

0;

s0,

=>

s2,

1;

s1,

=>

s0,

0;

s1,

=>

s2,

1;

s2,

=>

s2,

1;

s2,

=>

s3,

0;

s3,

=>

s3,

0;

s3,

=>

s1,

1;

ss,

Table .

=>

END;

ss,

END TABLE;

= clk;

END TABLE;
END;

ss 4 ,
(z).

4 .

2 .

Table .

D (DFF),

, moore1.tdf,

1.2.7.5

AHDL

.

,
Clock.

15

mealy.tdf,

FLEX

,
,

SUBDESIGN mealy

WHEN OTHERS Case ,

clk

: INPUT;

reset : INPUT;

: INPUT;

: OUTPUT;

WHEN.

VARIABLE

,
WHEN

OTHERS

ss: MACHINE WITH STATES (s0, s1, s2, s3);

BEGIN

ss.clk = clk;

ss.reset = reset;

n-
2n

TABLE
%

ss,

=> z,

ss;

recover.tdf,

=> 0,

s0;

=> 1,

s1;

s1,

=> 1,

s1;

s1,

=> 0,

s2;

SUBDESIGN recover

s2,

=> 0,

s2;

s2,

=> 1,

s3;

clk : INPUT;

s3,

=> 0,

s3;

go : INPUT;

s3,

=> 1,

s0;

ok : OUTPUT;

END TABLE;

s0,

s0,

2.

END;

VARIABLE
sequence : MACHINE
OF BITS (q[2..0])

1.2.7.6

WITH STATES (
idle,

one,

MAX+PLUS II, ,

two,

TDF.

three,

four,
illegal1,

illegal2,

illegal3);
BEGIN

. ,

sequence.clk = clk;

, ,

CASE sequence IS

WHEN idle =>

. Altera

IF go THEN

Case .

sequence = one;
END IF;
WHEN one =>
sequence = two;
WHEN two =>
sequence = three;

16

WHEN three =>

sequence = four;

WHEN OTHERS =>

(Function Prototype).

sequence = idle;

. MAX+PLUS

END CASE;

II

ok = (sequence == four);

END;

MAX+PLUS

(Include Files),

II

\maxplus2\max2lib\mega_lpm \maxplus2\max2inc,
3 : q2, q1, q0.

. Include ,

8 .

Include

5 , 3

TDF,

MAX+PLUS II.

1.2.8

macro1.tdf,

4- ,

TDF ,

4 16.

AHDL,

Variable .

Instance

, Altera- ,
INCLUDE "4count";

, .

INCLUDE "16dmux";
1.2.8.1

SUBDESIGN macro1

clk
MAX+PLUS

II

: INPUT;

out[15..0] : OUTPUT;

VARIABLE

MAX+PLUS

counter : 4count;

decoder : 16dmux;

\maxplus2\max2lib,

II

BEGIN

counter.clk = clk;

. AHDL.

counter.dnup = GND;

( . .

decoder.(d,c,b,a) = counter.(qd,qc,qb,qa);

out[15..0] = decoder.q[15..0];

AHDL:

END;

. .

Variable

Instance

Logic

TDF

4count

Variable

Logic .

Include ,

16dmux.

counter

4count, decoder

16dmux.

<

>.< >,
Instance

,
.

, , ID ,
.

Logic ,
.
macro2.tdf, ,
macro1.tdf,

q[3..0]:
INCLUDE "4count";
INCLUDE "16dmux";
SUBDESIGN macro2

17

(
clk

out[15..0] : OUTPUT;

(=)

VARIABLE
q[3..0]

: INPUT;

: NODE;

BEGIN
%

(q[3..0], ) = 4count (clk, , , , , GND, , , , );

(q[3..0], ) = 4count (.clk=clk, .dnup=GND);

4count

Logic .

,
%

%
%

RETURNS,

%
%

q[3..0]

4count

(.clk=clk,

.dnup=GND)

RETURNS

RETURNS

%
%

RETURNS (qd, qc, qb, qa);

out[15..0] = 16dmux (.(d, c, b, a)=q[3..0]);

.
%

1.2.8.2

% out[15..0] = 16dmux (q[3..0]); %

MAX+PLUS

END;

4count.inc

II

(LPM).

16dmux.inc :

RAM
FUNCTION 4count (clk, clrn, setn, ldn, cin, dnup, d, c,

b, a)

RETURNS (qd, qc, qb, qa, cout);

FUNCTION 16dmux (d, c, b, a)

RETURNS (q[15..0]);

4count 16dmux

.

4count

Logic ,

).

MAX+PLUS II

16dmux

\maxplus2\max2lib,

;
AHDL.

Instance

18

WITH,

WITH

FUNCTION lpm_add_sub(cin, dataa[LPM_WIDTH-1..0],

datab[LPM_WIDTH-1..0], add_sub)
WITH

RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

WITH

,
.

lpm_add1.tdf,

lpm_add_sub.

lpm_add_sub

LPM_WIDTH

LPM_REPRESENTATION.

lpm_add2.tdf,

lpm_add1.tdf, 8-
Instance .
INCLUDE "lpm_add_sub.inc";
SUBDESIGN lpm_add2
(
a[8..1], b[8..1] : INPUT;
c[8..1]

: OUTPUT;

carry_out

: OUTPUT;

VARIABLE
8bitadder : lpm_add_sub WITH (LPM_WIDTH=8,
LPM_REPRESENTATION="unsigned");
BEGIN
8bitadder.cin = GND

INCLUDE "lpm_add_sub.inc";

8bitadder.dataa[] = a[]

SUBDESIGN lpm_add1

8bitadder.datab[] = b[]

8bitadder.add_sub = GND

a[8..1], b[8..1] : INPUT;

c[] = 8bitadder.result[]

: OUTPUT;

carry_out

lpm_add1.tdf

8-

c[8..1]

LPM_WIDTH

. ,

LPM_REPRESENTATION,

ONE_INPUT_IS_CONSTANT)

, .

(LPM_WIDTH,

LPM_DIRECTION, ADDERTYPE,

carry_out = 8bitadder.cout

: OUTPUT;

END;

)
BEGIN

1.2.8.3

%
(c[], carry_out, ) = lpm_add_sub(GND, a[], b[],
GND,,)

TDF .

WITH (LPM_WIDTH=8,

LPM_REPRESENTATION="unsigned");

--(c[],carry_out,)=

TDF

lpm_add_sub(.dataa[]=a[],.datab[]=b[],
--

.cin=GND, .add_sub=GND)

-- WITH (LPM_WIDTH=8,

LPM_REPRESENTATION="unsigned");

END;
1.

lpm_add_sub

19

2.

MACHINE INPUT MACHINE

User Libraries ( Options)

Check ( File)

Include

Create Default

Include

File)

TDF

Include

TDF

Symbol

MACHINE

INPUT

ss_def.tdf,

ss
ss_out.

File)

(
clk, reset, count : INPUT;

ss_out

GDF .

,
TDF

SUBDESIGN ss_def

Choose Create
Default

Variable .

.
B.

Include

,
(

&

File

Save

Include ,

Include

Project

Create Default Include File ( File)

:
A.

.
I.

OUTPUT

: MACHINE OUTPUT;

VARIABLE
ss: MACHINE WITH STATES (s1, s2, s3, s4, s5);
BEGIN
ss_out = ss;

CASE ss IS

, Altera.

WHEN s1=>

1.2.8.4

WHEN s2=>

IF count THEN ss = s2; ELSE ss = s1; END IF;

IF count THEN ss = s3; ELSE ss = s2; END IF;

WHEN s3=>

TDF

IF count THEN ss = s4; ELSE ss = s3; END IF;

WHEN s4=>

MACHINE INPUT
MACHINE OUTPUT

Subdesign .

IF count THEN ss = s5; ELSE ss = s4; END IF;

WHEN s5=>

, ,
, ,

MACHINE.

IF count THEN ss = s1; ELSE ss = s5; END IF;

END CASE;
ss.(clk, reset) = (clk, reset);
END;

ss_use.tdf,

ss_in.
SUBDESIGN ss_use

20

sync
BEGIN

out

sm_macro.(clk, reset, count) = (sys_clk, !/reset, !

: OUTPUT;

hold);

BEGIN

sync.ss_in = sm_macro.ss_out;

out = (ss_in == s2) OR (ss_in == s4);

sync_out = sync.out;

END;

END;

top1.tdf,

1.2.9

ss_def ss_use.

ss_use

MACHINE,

ss_def

: ss_use;

ss_in : MACHINE INPUT;

LCELL & SOFT

( )

NODE

FUNCTION ss_def (clk, reset, count)

SOFT

. SOFT

RETURNS (MACHINE ss_out);

LCELL

LCELL

NODE

FUNCTION ss_use (MACHINE ss_in)

NODE

RETURNS (out);

Node

Variable

SUBDESIGN top1

NODE

sys_clk, /reset, hold : INPUT;

, .

sync_out

: OUTPUT;

VARIABLE

ss_ref:

MACHINE;

SOFT

BEGIN

, NODE
ss_ref = ss_def(sys_clk, !/reset, !hold);

sync_out = ss_use(ss_ref);

SOFT

END;

LCELL . SOFT

TDF

Variable . top2.tdf,

LCELL

, top1.tdf,

.
FUNCTION ss_def (clk, reset, count)
RETURNS (MACHINE ss_out);
FUNCTION ss_use (MACHINE ss_in)
RETURNS (out);

. LCELL

SUBDESIGN top2

LCELL ,

SOFT

LCELL

MAX+PLUS

II

sys_clk, /reset, hold : INPUT;

sync_out

SOFT LCELL

: OUTPUT;

VARIABLE
sm_macro : ss_def;

21

TDF

NODE

NODE

nodevar

SOFT

odd_parity

LCELL

csdpram
csfifo

FIFO

d0 $ d1 $ ... $ d8.
softbuf

lpm_rom

SOFT

LPM

; ;

;
RAM
. .

TDF

NODE

TDF

SOFT

:
1.2.11

SUBDESIGN nodevar

SUBDESIGN softbuf

VARIABLE

VARIABLE

odd_parity : NODE;

odd_parity : NODE;

BEGIN

BEGIN

odd_parity =

odd_parity =

d0 $ d1 $ d2$

SOFT(d0 $ d1 $ d2)

For

SOFT(d3 $ d4 $ d5)

$
d6 $ d7 $ d8;

SOFT(d6 $ d7 $ d8);

END;

END;

LPM

:
CONSTANT NUM_OF_ADDERS = 8;
(

RAM

II.

: INPUT;

c[NUM_OF_ADDERS..1], cout : OUTPUT;

MAX+PLUS

ROM

VARIABLE
sum[NUM_OF_ADDERS..1],
carryout[(NUM_OF_ADDERS+1)..1] : NODE;
BEGIN

carryout[1] = cin;

FOR i IN 1 TO NUM_OF_ADDERS GENERATE

sum[i] = a[i] $ b[i] $ carryout[i];

RAM

ROM MAX+PLUS II.

b[i]);

END GENERATE;

Altera

RAM ROM.

cout = carryout[NUM_OF_ADDERS+1];
c[] = sum[];

carryout[i+1] = a[i] & b[i] # carryout[i] & (a[i] $

Altera

a[NUM_OF_ADDERS..1], [NUM_OF_ADDERS..1],

AHDL)

SUBDESIGN iter_add

1.2.10 RAM & ROM

II

iter_add.tdf,

cin

MAX+PLUS

Generate

$
d3 $ d4 $ d5$

RAM

ROM

MAX+PLUS II:

END;

iter_add.tdf

For

Generate

lpm_ram_d
q
lpm_ram_io

carryout

I/O

22

 If Generate

For

Generate ,

If Generate TDF ,

, ,

LPM MAX+PLUS II.

mega_lpm

max2lib.

1.2.12

1.2.13 Assert

Assert

If Generate , , ,

, ,

Assert

. If Generate

,
.

Assert

condlog1.tdf,

output_b

If Generate

Assert

PARAMETERS (DEVICE_FAMILY);

SUBDESIGN condlog1

output_b : OUTPUT;

BEGIN

input_a : INPUT;
)

output_b = LCELL(input_a);

condlog2.tdf,

If Generate
Generate ,

If

MAX+PLUS II

DEVICE_FAMILY

USED

Assert

SUBDESIGN condlog2
(

Device

input_a : INPUT;

output_b : OUTPUT;
)
BEGIN
IF DEVICE_FAMILY == "FLEX8000" GENERATE
output_b = input_a;
ASSERT

,
.

If Generate .

PARAMETERS (DEVICE_FAMILY);

DEVICE_FAMILY,

Logic

Assign).

condlog1.tdf,

END;

USED,

Assert a.

END GENERATE;

For

Then IF a = VCC THEN c = d,

output_b = input_a;
ELSE GENERATE

Extractor)

Assert

IF DEVICE_FAMILY == "FLEX8K" GENERATE

(Netlist

REPORT "

FLEX8000"
SEVERITY INFO;
ELSE GENERATE
output_b = LCELL(input_a);

23

ASSERT (DEVICE_FAMILY == "FLEX10K")

REPORT "

AND
ASSERT
BEGIN
BIDIR
BITS
BURIED
CASE
CLIQUE
CONNECTED_PINS
CONSTANT
DEFAULTS
DEFINE
DESIGN
DEVICE
DIV
ELSE
ELSIF
END
FOR

%",

DEVICE_FAMILY;
END GENERATE;
END;

1.3

1.3.1

AHDL,

FUNCTION
GENERATE
GND
HELP_ID
IF
INCLUDE
INPUT
IS
LOG2
MACHINE
MOD
NAND
NODE
NOR
NOT
OF
OPTIONS
OR
OTHERS

OUTPUT
PARAMETERS
REPORT
RETURNS
SEGMENTS
SEVERITY
STATES
SUBDESIGN
TABLE
THEN
TITLE
TO
TRI_STATE_NODE
VARIABLE
VCC
WHEN
WITH
XNOR
XOR

GND
VCC.

CARRY
CASCADE
CEIL
DFFE
DFF
EXP
FLOOR
GLOBAL

.
Altera

('),

1.3.2

JKFFE
JKFF
LATCH
LCELL
MCELL
MEMORY
OPENDRN
SOFT

SRFFE
SRFF
TFFE
TFF
TRI
USED
WIRE
X

,
TDF .tdf.

1.3.3

Shift+F1 1

AHDL

_
/
-%
( )

( )
( )
( )
( )
( )
( )

.
VHDL
AHDL
. ,
(a, b, c) a, b, c.

Subdesign

.
,
Truth Table.
State Machine.

Parameters,

Instance Function
Prototype

24

 , Assert.
Define.
( )
( )
( )

[ ]
'...'
"..."

Title, Parameters, Assert.
Include.

( )

.
.
.
AHDL.
.
GND VCC

( )
( )
( )
( )

..
;
,
=

Subdesign.
Options.

Parameters

.
.
,
=>

( )

.
Truth Table.

+
==
!
!=

( )
( )
( )
( )
(

WHEN Case.

)
>
>=
<
<=
&
!&
$
!$
#
!#
?

( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )

-
-
- -

-
. :
< 1> ? < 2> : < 3>

( ),

.
3.

1.3.4

4.

AHDL :

5.

6.

7.

8.

A.

,
.

TDF:

B.

1.
2.

TDF .

25

C.

[]

. ,
a [4..1] a[].
b [6..0][3..2] b[][].
2.

, . . d[6..0][2..0].

(~),

(Fit

File)

32

ACF .

name[y][z]

, .

namey_z,

3.

, , (a, b,

('), .

c).

TDF ,

. ,

(pinstub).
reg DFF
reg.(d, clk, clrn, prn).
1.3.5

, ,

, 256

),

b[5..0]

(b5, b4, b3, b2, b1, b0)

b[]

GND VCC
.

b[log2(256)..1+2-1]

b[2^8..3 mod 1]

b[2*8..8 div 2]

:
1.

, . . a[4..1].

32

. ,
q[MAX..0] ,
MAX

1.3.5.1

(..)
[]. ,
a[4..1] a4, a3, a2, a1.
d[B"10"..B"00"] d2, d1, d0.

Constant.

26

 b4, b3, b2, b1.

b[2*2..2-1]

.
,

q[MAX..0]

MAX

Constant.

c[MIN(a,b)..0]

MIN

Define.

t[WIDTH-1..0]

WIDTH

1.3.6

AHDL

.
:

<

B"<
X- >"

"

c[5..1],

7>"

Q"<

7>"

X"<

0 9, A F>"
H"<

. ,

0 9, A F >"

0- , 1-

O"<

9>

( ).

")

Parameters.

:
1. MAX+PLUS II

;
.
2.

c[3..1]

c[4..2]

VCC GND.

c4
c[5]

1.3.7

(c2, , c4)

(c2,

c4),

Constant,

Define,

Parameters

. ,

BIT0

Options

SUBDESIGN foo
(
a[4..2+1-3+8] : INPUT;
)
,

27

CONSTANT foo = 1 + 2 DIV 3 + LOG2(256);

DEFINE MIN(a,b) = ((a < b) ? a : b);

/

:
+ ( )
- ( )
!
^
MOD
DIV
*
LOG2
+
== ( )
==

+1
-1
!a
a ^ 2
4 MOD 2
4 DIV 2
a * 2
LOG2(4-3)
1+1
1-1
5 == 5
"a" == "b"

NOT

1
1
1
1
2
2
2
2
3
3
4
4

( )
!=
>
>=
<
<=
&
AND
!&
NAND
$
XOR
!$
XNOR
#
OR
!#
NOR
?

5 != 4
5 > 4
5 >= 5
a < b+2
a <= b+2
a & b
a AND b
1 !& 0
1 NAND 0
1 $ 1
1 XOR 1
1 !$ 1
1 XNOR 1
a # b
a OR b
a !# b
a NOR b
(5<4) ? 3:4

AND

4
4
4
4
4
5

NAND

XOR

XNOR

OR

NOR

USED,

If Generate Parameters.
1.
.
2.

USED

LOG2

. , LOG2(257) = 9.

CEIL,

FALSE,

LOG2 DIV,

, 1.3.9.2.

1.3.8

AHDL

,
Define:

28

FLOOR,

AHDL

Equations

1.2.5.2

LOG2 DIV,

1.3.9.1

CEIL(LOG2(255)) = 8

Assert:
USED(aconst) == # 0 USED(AVALUE)

!tob

NOT
&
AND
!&
NAND

NOT tob
bread & butter
bread AND butter
a[3..1] !& b[5..3]
a[3..1]
NAND

#
OR
!#
NOR
$

b[5..3]
trick # treat
trick OR treat
c[8..5] !# d[7..4]
c[8..5] NOR d[7..4]
foo $ bar

XOR
!$

foo XOR bar

x2 !$ x4

XNOR

x2 XNOR x4

FLOOR(LOG2(255)) = 7

1.3.9

Case
If Then.

NOT (!),
1.

, a, b[5..1], 7, VCC

.
2.

, out[15..0] = 16dmux(q[3..0]);

, .
3.

(!

-),

, !c

lpm_add_sub

lpm_compare ,
4. ,

Use LPM for AHDL Operators .

, d1 $ d3
5.

, (!foo & bar)

1.3.9.1.1

NOT

.
, .

:

29

1. - , GND, VCC,

5. - ,

. , !a

, .

2. - ,

!a[4..1] (!a4, !a3, !

a2, !a1).

(a, b, c) & (0, 0, 1).

. ,

3.

(a,

b,

B"001"

c)

&

1,

(a & 0, b & 0, c & 1).

. , !9
!B"1001", B"0110".

, VCC
,

, 1 .

1.3.9.1.2

AND, NAND, OR, NOR,

, VCC .

XOR, XNOR

(a, b, c) & 1

(a, b, c) & VCC = (a, b, c)

:
1.

GND

VCC,

1.3.9.2

.
, (a & b).
2. - ,

,
.
.

(a,

b,

c)

(d,

e,

3. - , GND,

&

& b1).
4. - ,

(3

B"1000",

.
8),

B"0011"

:
:
+

+1

( )
- ( )
+

-a[4..1]
count[7..0]

delta[7..0]
rightmost_x[] -

leftmost_x[]

b[4..1]

(a & b4, a & b3, a & b2, a

f)

(a # d, b # e, c # f).
VCC,

= (0, 0, c)

B"1011".

30

 - ,
,

MAX+PLUS

count[7..0])

(0,

(0,

1.3.9.3

II

answer[7..0])
delta[7..0])

(cout,

+,

.
.

0
.

. , count[7..0]
delta[7..0]

cout:
:
== ( )
!= ( )
< (
<= (
> (
>= (

:
addr[19..4] == B"B800"
b1 != b3
fame[] < power[]
money[] <= power[]
love[] > money[]
delta[] >= 0

)
)
)
)

1.3.9.4

(X) .

MAX+PLUS

II

, ( 1 -

, VCC,

).

. ()

GND,

;
.
, . .,

1
1
2
2
3
3
3
3
3
3
4
4
5
5
6
6

/ :
- ( )
! ( )
+ ( )
- ( )
== ( )
!= ( )
< ( )
<= ( )
> ( )
>= ( )
& ()
!& ( - )
$ ( )
!$ ( - )
# ( )
!# ( - )

31

1.3.10

,
,

Hierarchy Down
MAX+PLUS

II

/LPM

1.3.10.1

File).

, LPM

(LPM)

Altera
lpm_and
lpm_bustri
lpm_clshift
lpm_constant
lpm_decode
busmux

lpm_inv
lpm_mux
lpm_or
lpm_xor
mux

(
LPM

2.1.0,

- ,

MAX+PLUS

LPM

II

( , AHDL, VHDL, EDIF).

,
lpm_abs
lpm_add_sub
lpm_compare

lpm_counter
lpm_mult

-
,
Altera.
.

(LPM) 2.1.0,

\maxplus2\max2lib\mega_lpm,

VHDL

Verilog

HDL

EDA

Altera

/
Altera

( )

FLEX

a8255
fft
rgb2ycrcb
ycrcb2rgb

pll

10K, FLEX 8000, FLEX 6000, MAX 9000, MAX 7000

HDL

a16450
a6402
a6850
a8237
a8251

lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_dff
lpm_tff

clklock
ntsc

csfifo
csdpram
lpm_ff
lpm_latch
lpm_shiftreg

\maxplus2\max2lib\mega_lpm,

,
,

Hierarchy Down ( File).

.

( Help, Megafunctions/LPM).

32

lpm_and ( )

Altera

FUNCTION lpm_and

lpm_and

(data[LPM_SIZE-1..0][LPM_WIDTH-1..0])

. lpm_and

WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[LPM_WIDTH-1..0])

.
:

data[]

LPM_SIZE x LPM_WIDTH

[]

result[

LPM_WIDTH.

]
:

LPM_WIDTH

data[][] result[]. AND

LPM_SIZE

AND

.
:

data[LPM_SIZE-1]_[LPM_WIDTH-

result[LPM_WIDTH-1]

1]
0XXX...
X0XX...
XX0X...
...
1111...

0
0
0
...
1

AHDL ,
,

Hierarchy Down ( File).

lpm_and

.
:

1.3.10.2

MAX+PLUS

II

300

/ .

33

EDAC

SSI

MAX+PLUS II.

1.3.10.3

MAX+PLUS

II

. AHDL VHDL

GDF

OrCAD

GDF , .

MAX+PLUS

(.gdf),

\maxplus2\max2lib\prim,

( pinstub)

n , n

(.tdf), VHDL (.vhd).

II.

Schematic

AHDL VHDL ,

0,
0,

1,
1,

2,

A[0..2],

B[0..2], C[0..2] INPUT,

OUTPUT AND2.

INPUT,

INPUTC,

OUTPUT, OUTPUTC, BIDIR, BIDIRC,

.

6 INPUT, 3

OUTPUT 3 AND2

AND2
A0, B0, C0.
AND2
A1, B1, C1.
AND2
A2, B2, C2.
A0, A1, A2
A0, A1, A2, .
0, 1, 2

n ,
,
n .

, ,
,

. ,

0, 1, 2, .

34

,
,

, ,

.
.

data

Clock

data ENA .
OE TRI
VCC ( ).

VCC GND.

MAX+PLUS

II.

, ,

CARRY

OPNDRN

CASCADE

SOFT

EXP

TRI

GLOBAL (SCLK) WIRE ( GDF)

LCELL (MCELL)

CLRN:

VCC ( )

PRN:

VCC ( )

ENA:

VCC ( )

DFF

SRFF

35

DFFE

SRFFE

JKFF

TFF

JKFFE

TFFE

LATCH

INPUT

MACHINE INPUT

OUTPUT

MACHINE OUTPUT

BIDIR

BIDIR INOUT

BIDIRC

( GDF)

INPUT IN

INPUTC ( GDF)

OUTPUT

OUT

OUTPUTC( GDF)

.
, VCC
GND,

BIDIR.

INPUT

, TDF

.

AND

NOR

BAND ( GDF)

NOT

BNAND ( GDF)

OR

SUBDESIGN top

BNOR ( GDF)

VCC ( GDF)

BOR ( GDF)

XNOR

foo, bar, clk1, clk2, c[4..0][6..0] : INPUT = VCC;

GND ( GDF)

XOR

a0, a1, a2, a3, a4

: OUTPUT;

b[7..0]

: BIDIR;

NAND

)
( GDF)

CONSTANT

TDF

PARAM

Title Block

MACHINE INPUT MACHINE OUTPUT

Subdesign. ,

TDF

. MACHINE

INPUT

MACHINE

OUTPUT

, Function Prototype

TDF.

1.3.11
-

. :

,

Subdesign.
,

Logic.

TDF,

, Instance

Logic.

State Machine
Logic.

Subdesign:
< >: < > [ = <
> ]

36

 Instance

.reset

.oe

TRI

, .

.in

CARRY, CASCADE, EXP, TRI,

Variable,

reg

OPNDRN,

Logic:

.out

SOFT,

GLOBAL,

LCELL

TRI, OPNDRN, SOFT, GLOBAL, LCELL

VARIABLE
reg : DFF;
BEGIN
reg.clk = clk
reg.d
out

= d
= reg.q

END;

Logic:
< >.< >
<

>

. < >
,
Subdesign TDF

<

>

(pinstub),

GDF.
, Altera,

(pinstub),

.q

.d

.t

.j

J JK

.k

K JK

.s

SR

.r

SR

.clk

.ena

.prn

.clrn

37

 Title
,

1.4 .

Display Controller .
255 ,

AHDL. AHDL

(Report

File).

(TDF - Text

(end-of-line)

(end-of-file).

Design File).

. :

Title

TITLE """EPM5130"" Display Controller";

Parameters

Include

Constant

Title.

Define

Function Prototype

Title

Assert

1.4.3

Subdesign

Parameters
Parameters

Variable

Logic

(an instance)

AHDL

Subdesign

Logic.

AHDL ,

Parameters:
PARAMETERS
(
FILENAME = "myfile.mif", -- optional default value
follows "=" sign
WIDTH,

(TDF - Text

AD_WIDTH = 8,

Design File).
1.4.2

AHDL.

Options

1.4.1

NUMWORDS = 2^AD_WIDTH
);

Title

Title

Parameters
:

(Report
File),

Parameters

PARAMETERS,

Title:

TITLE "Display Controller";

Title

.

;

Title

TITLE,

(=). , ,

- ,

WIDTH

; (

).

, ,
, Altera .

1. (an instance)
. ,

(an

instance),

(Instance

Declaration) (in-line

reference),

Parameters

(;).

. (GDF -

, ,

Graphic Design File)

Edit Ports/Parameters

Symbol,

, .

, .

.
1.

.
O

Parameters

Parameters Assign.

AHDL.
,

1.

Parameters

Global

Project

(Assignment&Configuration file - .acf) .

1.
, Parameters
(TDF),

PARAM

PARAMETERS

, .

FOO = BAR;

BAR = FOO;

,
.

);

1.4.4

,
:

Include
Include

.inc
.

Include:
INCLUDE "const.inc";

Include

:
Include
INCLUDE,

.inc- ,

Include

.inc.

, Include,

Include (;).

Include .inc- .

MAX+PLUSII

const.inc

INCLUDE const.inc;
Include

(TDF).

- .

Include

.
O

AHDL.

Prototype

Function

.inc.

(in-line

Parameters

Create Default Include File File.

Constant

.inc

.inc

Function Prototype

Define

.inc

.inc,

(Instance
reference) .

(TDF).

.inc.
Declaration)

Include

Include

Altera

Include

.inc .

.inc

Subdesign.
1.
1.4.5

1.

User

Libraries

Options.
1.

\maxplus2\max2lib\mega_lpm
\maxplus2\max2inc,

Constant

Constant

Constant:

CONSTANT UPPER_LIMIT = 130;

CONSTANT BAR = 1 + 2 DIV 3 + LOG2(256);

(TDF),

CONSTANT FOO = 1;
CONSTANT FOO_PLUS_ONE = FOO + 1;

.inc,
Project Save&Check
File

Constant

Constant

CONSTANT,

MAX,

, (=)

Subdesign:

) .
Constant (;).

DEFINE MAX(a,b) = (a > b) ? a : b;

, ,

SUBDESIGN

(TDF). ,

dataa[MAX(WIDTH,0)..0]: INPUT;

datab[MAX(WIDTH,0)..0]: OUTPUT;

Logic

UPPER_LIMIT

130.

BEGIN

datab[] = dataa[];

END;

Define

Constant .

Define

DEFINE,

Constant

(=)

, .

Define

Constant

(;).

O Constant

AHDL.

(TDF).

MIN_ARRAY_BOUND

MAX:

CONSTANT FOO = BAR;

CONSTANT BAR = FOO;

DEFINE MAX(a,b) = (a > b) ? a : b;

DEFINE MIN_ARRAY_BOUND(x) = MAX(0, x) +

1.4.6

Define

Define

1;

(evaluated

function) ,

,
,
.

Define

WITH

ONE_INPUT_IS_CONSTANT)
FUNCTION compare (a[3..0], b[3..0])
RETURNS (less, equal, greater);

LPM_REPRESENTATION,

RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

(LPM_WIDTH,

LPM_DIRECTION, ADDERTYPE,

Function

Prototype

Define

FUNCTION

Define

AHDL.

lpm_add_sub

compare.

1.4.7

Function Prototype.

. , ,

Function Prototype

cin,

dataa[LPM_WIDTH-1..0] datab[LPM_WIDTH-1..0];

, ,

a3,a2,a1,a0,b3,b2,b1 b0.

;
.

MAX+PLUSII.

RETURNS.

- less, equal greater.

(an instance)

Function

overflow

count

. Subdesign

result[LPM_WIDTH-1..0],

WIDTH

Prototype

MACHINE) ,

Function Prototype

Declaration)

(an

instance)

. :

(Instance

(in-line

FUNCTION ss_def (clock, reset, count)

RETURNS (MACHINE ss_out);

reference),

Function

Prototype.

lpm_add_sub

(cin,

1..0], datab[LPM_WIDTH-1..0],

dataa[LPM_WIDTH-

add_sub)

Prototype

Prototype

(;).
Function

:
FUNCTION

Function

AHDL

(in-line reference).

(Instance Declaration)
(in-line reference). , -

Function

Prototype,

,
.

,
JKFF:

Prototype

.inc,

MAX+PLUSII Create
Default

Include

File

File,

.inc,

.inc

\maxplus2\max2lib\mega_lpm

\maxplus2\max2inc .

Altera -, ,

(MSB - Most Significant Bit),

(LSB - Least Significant Bit) ,

( ,

(MSB - Most Significant Bit);

Include

RETURNS (q);

( ,

FUNCTION JKFF (k, j, clk, clrn, prn)

Options

JKFF:

Function

RETURNS (q);

BIT0,

FUNCTION JKFF (j, k, clk, clrn, prn)

Options

1.4.8

(LSB - Least Significant Bit).

BIT0=MSB,

BIT0=MSB

. BIT0=ANY

, ,

Options

OPTIONS, BIT0

Options

(;).

Options:
OPTIONS BIT0 = MSB;

(MSB).

LSB - ANY
-

 Options

Options

WIDTH %

Options

SEVERITY

ERROR,

WARNING INFO.
1.4.9

Assert

Assert

ERROR.

, ,

, ,

HELP_ID

Altera

Altera.
Assert

(;).

Assert:

Assert

Logic
AHDL.

ASSERT (WIDTH > 0)

"

REPORT

(%)

" WIDTH

1.4.10 Subdesign

SEVERITY

ERROR

HELP_ID

INTVALUE;

Subdesign

-- for internal Altera use only

Assert

Subdesign:

ASSERT

SUBDESIGN top
(

foo, bar, clk1, clk2

: INPUT = VCC;

, -

a0, a1, a2, a3, a4

: OUTPUT;

b[7..0]

: BIDIR;

REPORT,

REPORT

Subdesign

SUBDESIGN

REPORT

:
<severity>:

.
top.

<filename>: Assertion failed

<line

number>,

File

Line

INPUT)

( ,

7kadder: pterm_adder;

. ,

f, g

(;).

: NODE;

END GENERATE;

: INPUT,
OUTPUT, BIDIR, MACHINE INPUT
OUTPUT. ,

Variable

MACHINE

foo, bar, clk1 clk2, a0, a1, a2, a3

a4

. b[7..0]

.
MACHINE

OUTPUT

INPUT

MACHINE

. MACHINE INPUT

MACHINE OUTPUT

If Generate,

Variable

, , ,

GND VCC (

).

Variable

VCC ,

VARIABLE.

( ,

: NODE,

TRI_STATE_NODE,

<primitive>, <megafunction>, <macrofunction>

,

<state machine declaration>. ,

INPUT, OUTPUT BIDIR

a, b c, NODE; temp

halfadd;

tsnode TRI_STATE_NODE.

(;).
1.4.11 Variable

Variable

Logic.

.fit

AHDL ,

Variable:
VARIABLE
a, b, c

: halfadd;

ts_node : TRI_STATE_NODE;
IF DEVICE_FAMILY == "FLEX8000" GENERATE
8kadder: flex_adder;
d, e
ELSE GENERATE

: NODE;

(~).

.fit,

(.acf).

: NODE;

temp

, ( )
.

1.4.11.1

a[3..0], b[3..0]

: INPUT; --

less, equal, greater

:OUTPUT;--

,
.

a[8..1], b[8..1]

: INPUT; --

sum[8..1]

OUTPUT;--

.
-

Logic

comp

adder:

Function Prototype

comp.a[], comp.b[], comp.less, comp.equal,

comp.greater

adder.dataa[], adder.datab[], adder.result[]

. , -
,

( ,

.q

Function

Prototype.

SRFFE),

<primitive>,

JKFF,

JKFFE,

SRFF

( . ., .d, .t .in).

(..

<megafunction>

<macrofunction>.
,

.out)

Parameters.

1.4.11.2

AHDL

: NODE

TRI_STATE_NODE.

< >.< >

,
,

Subsection

adder compare,

. ,

VARIABLE

INPUT, OUTPUT BIDIR,

NODE TRI_STATE_NODE

comp : compare;

Subsection, ,

adder : lpm_add_sub WITH (LPM_WIDTH = 8);

comp

compare

adder

lpm_add_sub,

 .fit

TRI.

(~).

TRI_STATE_NODE:

INPUT

.fit,

OUTPUT BIDIR

(.acf).

BIDIR .

TRI_STATE_NODE

( ) .
.

1.4.11.3

, D, T, JK SR
SUBDESIGN node_ex

(DFF, DFFE, TFF, TFFE, JKFF, JKFFE, SRFF

SRFFE)

(LATCH).

a, oe

: INPUT;

: OUTPUT;

: BIDIR;

VARIABLE
ff : TFF;

)
VARIABLE

b : NODE;

- ,

t : TRI_STATE_NODE;

ff.

BEGIN

ff :

b = a;
out = b %

out = a %
ff.t

t = TRI(a, oe);
t = c;

ff.clk

% t c a %

ff.clrn

END;

ff.prn
NODE TRI_STATE_NODE

ff.q

NODE

( ,

.q

(..

Default :

VCC

SRFFE),

GND

JKFF,

JKFFE,

SRFF

( . ., .d, .t .in).
,

.out)

DFF : FUNCTION DFF(d, clk,

clr, prn) RETURNS (q); .

a = b a.d

TRI_STATE_NODE ,

= b.q:

NODE .
VARIABLE
a, b : DFF;

BEGIN

WITH STATES

a = b;

END;

Reset

1.4.11.4

(=)

. ,

s1

B000,

s2

B001

s3

B010.
VARIABLE

ss :

MACHINE

OF BITS (q1, q2, q3)

WITH STATES (

s1 = B"000",

s2 = B"010",

(;)

s3 = B"111");

ss. q1, q2 q3

s1, s2 s3,

q1, q2 q3.

<

>

2^< >

1.4.11.5

, ,

ss.

MACHINE.

OF BITS,
,

. :
FUNCTION ss_def (clock, reset, count)

q1, q2 q3.

RETURNS (MACHINE ss_out);

VARIABLE

BEGIN
ss = ss_def (sys_clk, reset, !hold);

IF ss == s0 THEN

s1, s2 s3.

ss : MACHINE;

WITH STATES,

ELSIF ss == s1 THEN
END;

Logic

BEGIN END. END

(;), .

Defaults,

MACHINE. ,

ss

AHDL

, NODE

Logic,

MACHINE INPUT MACHINE OUTPUT

1.4.12.1

Subdesign.

Logic

AHDL

, , -

.
ss_out

(;).
a[] = ((c[] & -B"001101") + e[6..1]) # (p, q, r, s, t,
MACHINE INPUT MACHINE
OUTPUT

v);

,
.

1.4.12 Logic

(TDF)

Logic

Case.

.
(=)

,
.
(=)

(==),

If Then.

, ,

If Generate

If Generate

Assert.

Defaults.

Logic

(!).

, ,

NOT

1.

B001101

B110011. (-)
.
1. B110011

c[].

1. ,

, e[6..1].
1. ,

(+) 0

(p, q, r, s, t, v).

a[ ].

count[7..0]

delta[7..0]

, ,

cout :

(cout,

answer[7..0])

(0,

count[7..0])

(0,

delta[7..0])

,
,

(#),

VCC.

a[4..1] = b[2..1]

.
, VCC GND

a4 = b2

a3 = b1

a2 = b2
a1 = b1

, (a, b) = e a = e b =

e.

. , (a, b)

= (c, d)

a = c b = d.

,
.

.
, (a, b) = 1 a = 0; b =1;

(a,
b, c, d) :
(a, , c, ) = B"1011";

1.

CASE f[].q IS

(;).

WHEN H"00" =>

addr[] = 0;

1.4.12.2

s = a & b;

WHEN H"01" =>

count[].d = count[].q + 1;

WHEN H"02", H"03", H"04" =>

Logic

f[3..0].d = addr[4..1];

Clock, Reset Clock Enable

WHEN OTHERS =>

f[].d = f[].q;

END CASE;

Case

:
ss.clk = clk1;
ss.reset = a & b;

ss.ena = clk1ena;

CASE IS

:

( ,

, f[ ].q).

Case

END CASE
Clock, Reset Clock Enable

(;).

<

>.<

ss.

>. , ,

Case

WHEN.

WHEN.

<

(=>).

>.clk

>.reset;

<

CASE,

(=>)

, f[ ].q h01,

count[ ].d

- ,

<

= count[ ].q + 1.
,

>.ena .

CASE

(;).

1.4.12.3

Case.

Case

, ,
CASE.

Case:

WHEN OTHERS.

, ,
f[ ].q

H00, H01

HCF,

f[ ].d = f[].q.
Defaults

,
WHEN OTHERS .

Default ,

- ,

Case

Default -

, .

, , a

n -

, y z

2^n ,

WHEN

OTHERS

WHEN

OTHERS

(a

VCC) Default.

(;).

Default

:
Defaults.

1.4.12.4

Logic
Defaults

Default

, If Then Case.

BEGIN.

GND,

Default

Default

- .

.
,

Default

Subdesign.

( )

NODE,

Defaults:

,
VCC.

BEGIN

(TDF)
DEFAULTS

a = VCC;

VCC:

IF y & z THEN
% a %

BEGIN

END IF;

DEFAULTS

END;

a = GND;
bn = VCC;

Defaults

END DEFAULTS;

:
IF c1 THEN

DEFAULTS

END

a = a1;

DEFAULTS.

bn = b1n;

(;).

END IF;

Defaults
,

GND bn

END DEFAULTS;

a = GND;

IF c2 THEN

a = a2;

, VCC

bn = b2n;

a.
(;).

END IF;
END;

addr[3..1] = f[3..1].q;

f[].d = addr[] + 1;

ELSIF g3 $ g4 THEN
f[].d = addr[];

a = c1 & a1 # c2 & a2;

ELSE

bn = (!c1 # b1n) & (!c2 # b2n);

d = VCC;
END IF;

,
,

VCC.

If

Then

reg[].clrn
VCC:

IF

THEN

SUBDESIGN 5bcount

d[5..1]

: INPUT;

THEN.

clk

: INPUT;

clr

: INPUT;

(;).

sys_reset

: INPUT;

enable

: INPUT;

load

: INPUT;

THEN

q[5..1]

: OUTPUT;

VARIABLE

reg[5..1]

THEN

ELSEIF

: DFF;

BEGIN

( ),

DEFAULTS
reg[].clrn = VCC;

THEN,

END DEFAULTS;

reg[].clk = clk;

q[]

= reg[];

ELSEIF

THEN

ELSE,

IF sys_reset # clr THEN

WHEN OTHERS

reg[].clrn = GND;

Case.

END IF;

,
!reg[].prn = (load & d[]) & !clr;

!reg[].clrn = load & !d[];

ELSE. ,

reg[] = reg[] + (0, enable);

,
,

END;

d = VCC.
1.4.12.5

If Then.

ELSE .
,

If

Then

IF THEN,
.

If Then:
IF a[] == b[] THEN
c[8..1] = H "77";

IF ELSEIF
.

If

Then

END IF (;).

If

Then

,
.

If

Generate

If Then

, a b ,

(;).

,
If:

If

Generate

GENERATE

ELSE GENERATE

IF a THEN

IF a THEN

c = d;

c = d;

END IF;

If Generate

ELSIF b THEN

IF !a & b THEN

c = e;

END GENERATE,

c = e;

ELSE

(;).

END IF;

If Generate

IF !a & !b THEN

Logic Variable.

c = f;

c = f;

END IF;

END IF;

If Then,

If Then,

, If Generate

Generate

If

Generate

Then If Generate

If Then If

If

),

( ),

If

Generate

For Generate,

, ,

1.4.12.6

If Generate

If

Generate

1.4.12.7

If Generate:

For Generate.

Generate:
IF DEVICE_FAMILY == "FLEX8K" GENERATE
c[] = 8kadder(a[], b[], cin);

CONSTANT NUM_OF_ADDERS = 8;

ELSE GENERATE
c[] = otheradder(a[], b[], cin);
END GENERATE;

SUBDESIGN 4gentst
(
a[NUM_OF_ADDERS..1], b[NUM_OF_ADDERS..1],

For

cin
c[NUM_OF_ADDERS..1], cout

: INPUT;

1.4.12.8

: OUTPUT;

(In-Line

Logic Function Reference).

VARIABLE

carry_out[(NUM_OF_ADDERS+1)..1] : NODE;

BEGIN

carry_out[1] = cin;

FOR i IN 1 TO NUM_OF_ADDERS GENERATE

c[i] = a[i] $ b[i] $ carry_out[i];

Logic

% %

carry_out[i+1] = a[i] & b[i] # carry_out[i] & (a[i] $

b[i]);

END GENERATE;

cout = carry_out[NUM_OF_ADDERS+1];

END;

Function

Prototype

For Generate

FOR GENERATE

1. ,

For

Generate

b[3..0],

1. IN ,
.

less,

cin

equal,

add_sub,

result[LPM_WIDTH-1..0],

cout overflow.
FUNCTION compare (a[3..0], b[3..0])
RETURNS (less, equal, greater);

_sub.

lpm_add

lpm_add_sub

TO.

Function

NUM_OF_ADDRESS.

greater;

a[3..0]

dataa[LPM_WIDTH-1..0],

compare

compare

Prototype

i.

. ,

FUNCTION

(cin,

dataa[LPM_WIDTH-

WITH (LPM_WIDTH, LPM_REPRESENTATION)

RETURNS

.
GENERATE

lpm_add_sub

1..0], datab[LPM_WIDTH-1..0], add_sub)

(result[LPM_WIDTH-1..0],

cout,

overflow);

(;).

references)

(in-line

If Generate

function

END GENERATE,

lpm_add_sub

(;).

logic

compare

(clockwise, , counterclockwise) = compare(position[],

target[]);

sum[] = lpm_add_sub (.datab[] = b[], .dataa[] = a[])

WITH (LPM_WIDTH = 8)

RETURNS (.result[]);

WITH

,
;

(=)

Parameters.

position[] target[]

8.

LPM_WIDTH

compare,

lpm_add_sub,

compare less greater

a[3..0] b[3..0].

counterclockwise

clockwise

lpm_add_sub

. compare
equal

result[]

sum[]

- Logic,

. ,

lpm_add_sub, .datab[]
.dataa[]

b[]

a[]

compare,

position[]

target[] ,

clockwise

compare.

less

greater

counterwise,

(=).

Logic.

1.
.< > ,

Truth Table.

1.4.12.9

.
1.

Truth

Table

, AHDL

, .


Truth Table:

END

TABLE,

(;).
TABLE
a0,

f[4..1].q

=> f[4..1].d, control;

:
0,

B"0000" => B"0001", 1;

0,

B"0100" => B"0010", 0;

1,

B"0XXX" => B"0100", 0;

X,

B"1111" => B"0101", 1;

, .

END TABLE;

Truth

Table

. X
,

a0

(=>)

. ,

(;).

f4

TABLE,

.
,

X:

. , ,

TABLE

a0 f[4..1].q;

a0,

f[4..1].q => f[4..1].d, control;

0,

B"0000" => B"0001", 1;

0,

B"0100" => B"0010", 0;

1,

B"0XXX" => B"0100", 0;

X,

B"1111" => B"0101", 1;

f[4..1]

control.

END TABLE;

(;).

(=>).

. ,

, , ,

a0

0, f[4..1].q

B0000, f[4..1].d

B0001,

control 1.

(..

X
(

).

,
.

, VCC

GND,

1.5
1.6
1.7
1.8 -

. tdf.
-

:
(
)