Embedded System Design with FPGAs using HDLs(Lessons learned and pitfalls to be avoided)
R James Duckworth
Electrical & Computer EngineeringWorcester Polytechnic InstituteWorcester, MA 01609
rjduck@wpi.edu
Abstract
This paper describes the authors experience withteaching VHDL (and more recently, Verilog) toundergraduate and graduate students at WPI and toengineers through various short courses in industry.The courses have concentrated on logic synthesistargeting CPLDs and FPGAs. All the courses had amajor lab component where students could usesimulation tools to test their design using test benchesand also synthesis tools to synthesize, implement, and download the configuration bit-stream to evaluationboards. The paper concentrates on some of the problems that students encounter when they are tryingto design their digital systems using HDLs. In additionto the conceptual issues with using a language todescribe hardware behavior, the newer higher capacity devices provide additional challenges as more functions, including embedded processors, are added to the device.
1. Introduction
This paper summarizes the main issues that seem tocause problems for students when they are learning touse VHDL or Verilog to describe hardware for the firsttime. While there have been many books written thatcover VHDL (and to a lesser extent Verilog), mostseem to confuse students more than help them andinvariably end up mixing constructs that are onlysuitable for synthesis with other language capabilitiesthat should only be used for simulation. Having usedVHDL on many research projects and taught manycourses over the years the author has adopted a plan totry to alleviate the most common problems forstudents. In the examples given below it should benoted that reference is made to VHDL, however theprinciples apply just as well to other HDLs such asVerilog.
2. Synthesis or modeling first?
Most text books start out by describing the use of VHDL for modeling digital components and systemsby using many features of the language includingadding in time related information. Instead of thisapproach, the author has always started by introducingand only covering the subset of VHDL suitable forsynthesis. This approach is further helped by providingstandard templates and vendor recommendations fordescribing combinational and sequential logic,including state machines. Only after VHDL forsynthesis has been thoroughly explained, and multipleexamples and designs attempted, are the additionalkeywords and constructs covered that are appropriatefor testing, simulation and modeling. This approachseems to minimize confusion and stops students fromtrying to use inappropriate statements when they areusing VHDL for synthesis.
3. VHDL is not a programming language.
When introducing VHDL, it is very important to keepemphasizing the fact that the VHDL code is only
describing
the required behavior of the digital circuitor system and is not being executed in some way by a‘hidden’ interpreter or microprocessor on the FPGA.A clear distinction needs to be made between a VHDLdescription that will be
synthesized
by the tools toproduce a hardware implementation and the samedescription that will be
simulated
on a conventionalcomputer. It is useful to describe the hardware featuresof the target device (for FPGAs, this would be look-uptables for combinational logic, and flip-flops forsequential circuits) and to explain that the VHDLdescription will be analyzed, compiled, andsynthesized to these hardware components, and the bit-stream sent to the device is just a configuration file.Unfortunately, with the recent capability to routinely
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