Edge-Triggered Flip-flops

S-R, D and J-K edge-triggered flip-flops. Note

the > symbol at the clock input.
S C R Q' Q D C Q' Q J C K Q' Q

Positive edge-triggered flip-flops

S C D C J C

Q'

Q'

Q'

Negative edge-triggered flip-flops

S-R Flip-flop
S-R flip-flop: on the triggering edge of the clock
pulse,
S=HIGH (and R=LOW) a SET state R=HIGH (and S=LOW) a RESET state both inputs LOW a no change both inputs HIGH a invalid

Characteristic table of positive edge-triggered S-R

flip-flop:
S 0 0 1 1 R 0 1 0 1 CLK X Q(t+1) Q(t) 0 1 ? Comments No change Reset Set Invalid

X = irrelevant (dont care) = clock transition LOW to HIGH

S-R Flip-flop
It comprises 3 parts:
a basic NAND latch a pulse-steering circuit a pulse transition detector (or edge detector) circuit

The pulse transition detector detects a rising (or

falling) edge and produces a very short-duration spike.

S-R Flip-flop
The pulse transition detector.
S CLK Pulse transition detector R Q

Q'

CLK'
CLK CLK* CLK CLK' CLK* CLK

CLK'
CLK* CLK CLK' CLK*

Positive-going transition (rising edge)

Negative-going transition (falling edge)

FLIP-FLOP TYPES
RS FLIP FLOP (Reset/Set) a.k.a. Set/Clear

S CLK R

Q Q

Most basic flip flop can be made by cross coupling NAND or NOR gates Activating Set and Reset is invalid

D Flip Flop (Data or Delay)

D CLK

Q Q

Has only a single data input and clock input Input transfers to output on clock pulse

T Flip Flop (Toggle)

Q T Q

Output toggles on each clock pulse Q output divides clock frequency in half

J-K Flip Flop

J CLK K

Q Q

Universal, can make all other flip flops Has no prohibited states

POSITIVE LEVEL TRIGGERED

D

DQ FLIP-FLOP
CLK

Symbol:
D Q Q

Q NOT

EN

Truth Table:
EN 0 1 1 D X 0 1 Q* No change 0 1

*Q follows D input while EN is HIGH

POSITIVE LEVEL TRIGGERED

D FLIP-FLOP TIMING DIAGRAMS
D EN Q Q

C D Q

EN 0 1 1

D X 0 1

Q* No change 0 1

C D Q C D Q

*Q follows D input while EN is HIGH

POSITIVE EDGE TRIGGERED

D FLIP-FLOP TIMING DIAGRAMS
D CLK Q Q

C D Q

CLK

D X 0 1

Q* No change 0 1

C D Q C D Q

*Q follows D input when CLK is HIGH

D Clock

Qa

Gated D Latch
Clk Q Qa

Note that the Latch, Positive Edge-triggered FF, and Negative Edge-triggered FF each have a unique symbol

Q Q

Qb Qb

Positive Edge-triggered D Flip-Flop

Q Q

Qc

Negative Edge-triggered
Qc

D Flip-Flop

(a) Circuit
Clock
D Qa Qb Qc Gated D Latch + Edge-triggered D FF - Edge-triggered D FF

(b) Timing diagram

NEGATIVE EDGE TRIGGERED

T FLIP-FLOP
Symbol:
D Q

Q T Q

CLK Q

Output toggles on each clock pulse Q output divides clock frequency in half

Usually made with JK Flip Flop

Truth Table:
CLK Q QO Q= QO MEANS THAT THE NEW VALUE OF Q WILL BE THE INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT

NEGATIVE EDGE TRIGGERED

T FLIP-FLOP
Timing Diagrams
Q T Q

T Q
Q QO

CLK

T Q

Q= QO
CLK Q MEANS THAT THE NEW VALUE OF Q WILL BE THE QO INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT Q= QO MEANS THAT THE NEW VALUE OF Q WILL BE THE INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT

T Flip-flop
Application: Frequency division.
High J CLK C K CLK Q CLK QA QB Q CLK High J C K QA High J C K QB

Divide clock frequency by 2.

Divide clock frequency by 4.

T Flip-Flop

J-K FLIP-FLOP
UNIVERSAL Flip Flop can make all others from JK (T, D and RS)

J CLK K

Q Q

The J input acts like SET, K acts like RESET No illegal state, activating both inputs causes Q to TOGGLE

J-K FLIP-FLOP
J CLOCK

Symbol:

Q NOT

J CLK K

Q Q

Truth Table:
CLK 0 1 J X X X 0 0 1 1 K X X X 0 1 0 1 Q NO CHG NO CHG NO CHG NO CHG 0 1 QO MODE HOLD HOLD HOLD HOLD RESET SET TOGGLE

NEGATIVE EDGE TRIGGERED

J-K FLIP-FLOP
Timing Diagrams
J CLK K
CLK J 0 0 1 1

Q Q

C J K Q

K Q 0 NO CHG 1 0 1 0 1 QO

C J K Q

POSITIVE EDGE TRIGGERED

J-K FLIP-FLOP
Timing Diagrams
J CLK K
CLK J 0 0 1 1

Q Q

C J K

K Q 0 NO CHG 1 0 1 0 1 QO

C J K Q

C J K Q

ASYNCHRONOUS OVERRIDES
Asynchronous Inputs a.k.a. Overide Inputs operate independent of the control and clock inputs

PRE
J CLK K Q Q

PRE

PRESET Active-low override Q=1 overrides all other inputs

CLR

CLR

CLEAR

Active-low override Q=0

overrides all other inputs

J-K FLIP-FLOP
ASYNCHRONOUS OVERRIDES

PRE
J CLK K Q Q

CLR

PRE 1 1 0 0

CLR 1 0 1 0

Q* No effect; FF can respond to J, K, and CLK Q=0 independent of synchronous inputs Q=1 independent of synchronous inputs Ambiguous (not used)

*CLK can be in any state

J-K FLIP-FLOP
J Q

Symbol: Truth Table:

Mode of Operation Inputs PS Asynchronous set 0 Clr 1 Clk x J x K x Outputs Q 1 Q 0

Clk __
K Q

Asynchronous reset
Prohibited

1
0

0
0

x
x

x
x

x
x

0
1

1
1

------------------------------------------------------------------------Hold Reset Set Toggle x = Irrelevant = H-to-L transition of clock pulse 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 no change 0 1 1 0

opposite

J-K FLIP-FLOP ASYNCHRONOUS OVERRIDES Timing Diagrams

PRE
J CLK K Q Q

CLOCK PRESET CLEAR J K Q

CLR

PRE 1 1 0 0

CLR 1 0 1 0

Q No effect Q=0 Q=1 Illegal

Asynchronous Inputs
A J-K flip-flop with active-LOW preset and clear
inputs.PRE
J PRE Q Pulse transition detector Q'

J C K

Q
CLK

Q'

K CLR

CLR CLK PRE CLR

J = K = HIGH

Preset

Toggle

Clear

2 bit Asynchronous counter

3 bit Asynchronous counter

4 bits data store