Plaintiff’s Exhibit 1: Rambus’s Proposed Set of 35 Claims
- 1 -PATENT NO. 6,034,918
METHOD OF OPERATING A MEMORY HAVING A VARIABLE DATA OUTPUTLENGTH AND PROGRAMMABLE REGISTER1. A method of controlling a synchronous memory device, wherein the memory deviceincludes a plurality of memory cells, the method of controlling the memory devicecomprises:providing first block size information to the memory device, wherein the firstblock size information defines a first amount of data to be output by the memorydevice onto a bus in response to a read request; andissuing a first read request to the memory device, wherein in response to the firstread request, the memory device outputs the first amount of data corresponding tothe first block size information onto the bus synchronously with respect to anexternal clock signal.8. The method of claim 1 further including providing a code which is representative of adelay time to transpire before data is output onto the bus after receipt of a read request,wherein the memory device stores the code in an access time register on the memorydevice.
Case3:10-cv-05449-RS Document89-1 Filed05/03/12 Page2 of 14