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WHAT’S A DIGITAL SYSTEM?
1.1 Framing the digital design domain
1.1.1 Digital domain as part of electronics
1.1.2 Digital domain as part of computer science
1.2 Simple introductory examples
1.3 Diﬀerent embodiment of digital systems
1.4 Correlated domains
1.5 Problems
LET’S TALK IN VERILOG!
2.1 Pseudo-code languages & algorithms
2.2. FINITE INPUT VS. “INFINITE” INPUT ALGORITHMS 27
2.2 Finite input vs. “inﬁnite” input algorithms
2.3 History free systems & combinational circuits
2.4 History sensitive systems & sequential circuits
2.5 Time restrictions in digital systems
2.5.1 Pipelined connections
2.5.2 Fully buﬀered connections
2.6 Concluding about Verilog & digital systems
2.7 Problems
3.2 Growing the size by composition
3.3 Speeding by pipelining
3.3.1 Register transfer level
3.3.2 Pipeline structures
3.3.3 Data parallelism vs. time parallelism
3.4 Featuring by closing new loops
3.4.1 ∗ Data dependency
3.4.2 ∗ Speculating to avoid limitations imposed by data dependency
3.5. CONCLUDING ABOUT COMPOSING & PIPELINING & LOOPING 81
3.5 Concluding about composing & pipelining & looping
3.6 Problems
3.7 Projects
4.1 Loops & Autonomy
4.2 Classifying Digital Systems
4.3 # Digital Super-Systems
4.4 Preliminary Remarks On Digital Systems
4.5 Problems
4.6 Projects
5.2 How toyMachine works
5.4 Problems
5.5 Projects
Zero order, no-loop digital systems
6.1 Simple, Recursive Deﬁned Circuits
6.1.1 Decoders
Informal deﬁnition
Formal deﬁnition
Recursive deﬁnition
Structural description
Arithmetic interpretation
Application
6.1.2 Demultiplexors
6.1.3 Multiplexors
Structural aspects
6.1.4 ∗ Shifters
6.1.5 ∗ Priority encoder
6.1.6 Increment circuit
6.1.8 ∗ Combinational Multiplier
6.1.9 Arithmetic and Logic Unit
6.1.10 Comparator
6.1.11 ∗ Sorting network
Bathcer’s sorter
6.1.12 ∗ Preﬁx computation network
6.1.13 ∗ First detection network
6.1.14 ∗ Spira’s theorem
6.2 Complex, Randomly Deﬁned Circuits
6.2.1 An Universal circuit
6.2.2 Using the Universal circuit
6.2.3 The many-output random circuit: Read Only Memory
6.3. CONCLUDING ABOUT COMBINATIONAL CIRCUITS 157
6.4 Problems
6.5 Projects
First order, 1-loop digital systems
7.1 Stable/Unstable Loops
7.2 Elementary Structures
7.2.1 Elementary Latches
7.2.2 Elementary Clocked Latches
7.2.3 Data Latch
7.3 The Serial Composition: the Edge Triggered Flip-Flop
7.3.1 The Master-Slave Principle
7.3.2 The D Flip-Flop
7.3.3 The Serial Register
7.4 The Parallel Composition: the Random Access Memory
7.4.1 The n-Bit Latch
7.4.2 Asynchronous Random Access Memory
Expanding the number of bits per word
Expanding the number of words by two dimension addressing
7.5 The Serial-Parallel Composition: the Register
7.6 Applications
7.6.1 Synchronous RAM
7.6.2 Register File
7.6.3 Field Programmable Gate Array – FPGA
The system level organization of an FPGA
The IO interface
The switch node
The basic building block
The conﬁgurable logic block
7.6.5 ∗ An Associative Memory
7.6.6 ∗ Beneˇs-Waxman Permutation Network
7.6.7 ∗ First-Order Systolic Systems
7.7. CONCLUDING ABOUT MEMORY CIRCUITS 199
7.8 Problems
7.9 Projects
Second order, 2-loop digital systems
8.1. OPTIMIZING DFF WITH AN ASYNCHRONOUS AUTOMATON 209
8.1 Optimizing DFF with an asynchronous automaton
8.2 Two States Automata
8.2.1 The Smallest Automaton: the T Flip-Flop
8.2.2 The JK Automaton: the Greatest Flip-Flop
8.2.3 ∗ Serial Arithmetic
8.2.4 ∗ Universal 2-input and 2-state automaton
8.3 Functional Automata: the Simple Automata
8.3.1 Counters
8.3.2 ∗ Accumulator Automaton
8.3.3 ∗ Sequential multiplication
8.3.4 ∗ “Bit-eater” automaton
8.3.5 ∗ Sequential divisor
8.4 ∗ Composing with simple automata
8.4.1 ∗ LIFO memory
8.4.2 ∗ FIFO memory
8.4.3 ∗ The Multiply-Accumulate Circuit
8.5. FINITE AUTOMATA: THE COMPLEX AUTOMATA 229
8.5 Finite Automata: the Complex Automata
8.5.1 Basic Conﬁgurations
8.5.2 Designing Finite Automata
8.5.3 ∗ Control Automata: the First “Turning Point”
Verilog descriptions for CROM
Binary code generator
8.6 ∗ Automata vs. Combinational Circuits
8.7 ∗ The Circuit Complexity of a Binary String
8.9 Problems
8.10 Projects
Third order, 3-loop digital systems
9.1. IMPLEMENTING FINITE AUTOMATA WITH ”INTELLIGENT REGISTERS” 261
9.1 Implementing ﬁnite automata with ”intelligent registers”
9.1.1 Automata with JK “registers”
9.1.2 ∗ Automata using counters as registers
9.2 Loops closed through memories
Version 1: the controlled Arithmetic & Logic Automaton
Version 2: the commanded Arithmetic & Logic Automaton
9.3 Loop coupled automata: the second ”turning point”
9.3.1 ∗ Push-down automata
9.3.2 The elementary processor
9.3.3 Executing instructions vs. interpreting instructions
Von Neumann architecture / Harvard architecture
9.3.4 An executing processor
The organization
The instruction set architecture
INSTRUCTION SET ARCHITECTURE
Implementing toyRISC
The time performance
9.3.5 ∗ An interpreting processor
Microarchitecture
Instruction set architecture (ISA)
Implementing ISA
10.2.2 ∗ The micro-architecture
10.2.3 ∗ The instruction set architecture
10.2.4 ∗ Implementation: from micro-architecture to architecture
10.2.5 ∗ Time performances
10.2.6 ∗ Concluding about our Stack Processor
10.3 Embedded computation
10.3.1 The structural description of toyMachine
The top module
The interrupt unit
The control section
The data section
Multiplexors
10.3.2 Interrupt automaton: the asynchronous version
10.4 Problems
10.5 Projects
N-th order digital systems
11.1 Push-Down Stack as n-OS
11.2 Cellular automata
11.2.1 General deﬁnitions
The linear cellular automaton
The two-dimension cellular automaton
11.3 Systolic systems
11.4 Interconnection issues
11.4.1 Local vs. global connections
Memory wall
11.4.2 Localizing with cellular automata
11.4.3 Many clock domains & asynchronous connections
11.5 Neural networks
11.5.1 The neuron
11.5.2 The feedforward neural network
11.5.3 The feedback neural network
11.5.4 The learning process
Unsupervised learning: Hebbian rule
Supervised learning: perceptron rule
11.5.5 Neural processing
11.6 Problems
# ∗ GLOBAL-LOOP SYSTEMS
12.1 Global loops in cellular automata
12.3 Low level functional description
12.3.1 System initialization
12.3.3 Setting functions
12.3.4 Transfer functions
Basic transfer functions
12.3.5 Arithmetic functions
12.3.6 Reduction functions
12.3.7 Test functions
12.3.8 Control functions
12.3.9 Stream functions
12.4 Index
12.5 Problems
Pseudo-code language
Boolean functions
B.1 Short History
B.2 Elementary circuits: gates
B.2.1 Zero-input logic circuits
B.2.2 One input logic circuits
B.2.3 Two inputs logic circuits
B.2.4 Many input logic circuits
B.3 How to Deal with Logic Functions
B.4 Minimizing Boolean functions
B.4.1 Canonical forms
B.4.2 Algebraic minimization
Minimal depth minimization
Multi-level minimization
Many output circuit minimization
B.4.3 Veitch-Karnaugh diagrams
Minimizing with V-K diagrams
Minimizing incomplete deﬁned functions
V-K diagrams with included functions
B.5 Problems
Basic circuits
C.1 Actual digital signals
C.2 CMOS switches
C.3 The Inverter
C.3.1 The static behavior
C.3.2 Dynamic behavior
C.3.3 Buﬀering
C.3.4 Power dissipation
C.4 NAND & NOR gates
C.5 AND-NOR gates
C.6 Many-Input Gates
C.7 The Tristate Buﬀers
C.8 The Transmission Gate
C.9 # Memory Circuits
C.9.1 Flip-ﬂops
C.9.2 Static memory cell
C.9.3 Array of cells
C.9.4 Dynamic memory cell
Standard cell libraries
D.1 Main parameters
D.2 Basic cells
D.2.1 Gates
Two input AND gate: AND2
Two input OR gate: OR2
Three input AND gate: AND3
Three input OR gate: OR3
Four input AND gate: AND4
Four input OR gate: OR4
Four input AND-OR gate: ANDOR22
Invertor: NOT
Two input NAND gate: NAND2
Two input NOR gate: NOR2
Three input NAND gate: NAND3
Three input NOR gate: NOR3
Four input NAND gate: NAND4
Four input NOR gate: NOR4
Two input multiplexer: MUX2
Two input inverting multiplexer: NMUX2
Two input XOR: XOR2
D.2.2 # Flip-ﬂops
Finite Automata
E.1 Basic deﬁnitions in automata theory
E.2 How behaves a ﬁnite automata
E.3 Representing ﬁnite automata
E.3.1 Flow-charts
The ﬂow-chart for a half-automaton
The ﬂow-chart for a Moore automaton
The ﬂow-chart for a Mealy automaton
E.3.2 Transition diagrams
Transition diagrams for half-automata
Transition diagrams Moore automata
Transition diagrams Mealy automata
E.3.3 Procedures
HDL representations for Moore automata
HDL representations for Mealy automata
E.4 State codding
E.4.1 Minimal variation encoding
E.4.2 Reduced dependency encoding
E.4.3 Incremental codding
E.4.4 One-hot state encoding
E.5 Minimizing ﬁnite automata
E.6 Parasitic eﬀects in automata
E.6.1 Asynchronous inputs
E.6.2 The Hazard
Propagation hazard
Dynamic hazard
E.7 Fundamental limits in implementing automata
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