Bao Cao Game Fix

Final Report Bomberman Game on DE1 board
HA NOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

SHOOL OF ELECTRONIC AND TELECOMMUNICATION
EMBEDDED SYSTEM AND RECONFIGURABLE COMPUTING LAB
VHDL TRAINING COURSE

2012
Project:
BOMBERMAN ON FPGA
Trainers:
Ngoc A. Le
Khanh V. Nguyen
Hai N. Nguyen
Ha Noi, July 27, 2012

Group 1- K54 ESRC LAB
Page 1
Mc Lc
A.
LI NI U. ...................................................................................................4
B.
NI DUNG. ........................................................................................................5
1.Tng Quan ti. ....................................................................................................5

1.1. ti. ...............................................................................................................5
1.2. Yu cu ca ti. ...........................................................................................5
1.2.1. Yu cu chc nng. ...................................................................................5
1.2.2. Yu cu phi chc nng. .............................................................................5
1.3. M t tr chi. ..................................................................................................6
1.3.1.M t cch chi. .........................................................................................6
1.3.2.Tnh im. ..................................................................................................6
1.3.3.Kt thc. .....................................................................................................7
1.4. K hoch thc hin v phn cng cng vic. ...................................................7
1.4.1. K hoch thc hin....................................................................................7
1.4.2. Phn cng cng vic..................................................................................8
2. Gii thiu Cng ngh s dng. ...............................................................................8
2.1. Phn cng. ........................................................................................................8
Kit DE1 ..........................................................................................................8
2.2. Phn mm Quartus II 9.1. ..............................................................................10
2.3. Quy trnh thit k FPGA vi Quartus II.........................................................10
3. S khi ca h thng. .......................................................................................11
3.1.Bn phm .........................................................................................................12
Page 2

3.2.Mn hnh .........................................................................................................12
3.3.ROM ................................................................................................................12
3.4.Khi x l ( CU ) ............................................................................................12
4. Cc bc xy dng tng khi ca GAME. ...........................................................12
4.1. PS2 Keyboard.................................................................................................12
4.1.1.Khi nhn d liu PS2 .............................................................................12
4.1.2.Mch giao tip vi PS2 Keyboard. ..........................................................16
4.2. Khi VGA. .....................................................................................................19
4.2.1. h a ......................................................................................................19
4.2.2. iu khin video .................................................................................20
4.2.3. VGA text. ................................................................................................25
4.3. Khi di chuyn. ..............................................................................................28
4.4 Khi t bom. ..................................................................................................29
4.5. Khi hin th TEXT. .....................................................................................30
C.
KT LUN .......................................................................................................34
1.
Kt qu t c. .........................................................................................34
2.
Kh khn......................................................................................................34
3.
Xut. .......................................................................................................34
Ph lc .......................................................................................................................35
Ti liu tham kho .....................................................................................................36
Page 3

A. LI NI U.
VHDL l mt ngn ng m t phn cng cho cc mch tch hp tc cao vi
nhiu u im vt tri v c ng dng trong nhiu lnh vc m quan tr ng nht
l trong cc thit b logic c th lp trnh c nh FPGA, PLD
Vi vic vn dng nhng kin thc v VHDL qua cc bi lab altera chng em
c lm trc kt hp vi cc ti liu tham kho v lp trnh VHDL nng cao
ng dng lm game nh l game bomberman.
Em xin chn thnh by t lng bit n su sc ti TS Phm Ng c Nam, ti tt c
cc anh v cc bn ti lab ESRC, c bit anh V Quang Tr ng, anh V Hu Tip
tn tnh hng dn cho nhm chng em, to iu kin cho b n em nghin cu,
h c tp trong h c k h. Nhng li nhc nh, nhn xt ca cc anh gip cho em
tin b rt nhiu v c th thc hin nt dung thc tp mt cch tt nht.
Do kh nng cn hn ch v s lng cng logic trn DE1 l c hn nn trong
qu trnh lm Game c th khng trnh khi nhng thiu st v gin lc. Mong
cc anh v cc bn ch bo v ng gp thm kin nhm em c th hon thin
Project ny mt cch ti u nht.
Page 4
B. NI DUNG.
1.Tng Quan ti.
1.1. ti.
Sau khi hon thnh cc bi lab thc hnh trn Kit DE1 ca Altera, chng em
tip tc pht trin k nng thit k v vn dng vo thc t, l trin khai mt h
thng hon chnh trn Kit DE1 vi ti: Bomberman on FPGA
1.2. Yu cu ca ti.
1.2.1. Yu cu chc nng.
- Thc hin trn KIT DE1 ca ALTERA
- Mn hnh hin th VGA 640x480 pixels
- Bn phm chun PS/2
- Audio codec W871 (trn kit)
- Ngn ng VHDL s dng clock 50Mhz.
1.2.2. Yu cu phi chc nng.
- Yu cu giao din n gin, d chi, di chuyn mt.
- Tit kim c ti nguyn trn kit de1 ti a.
Page 5

1.3. M t tr chi.
1.3.1.M t cch chi.
Bt u mi vn u, ngi chi 1 xut hin gc trn bn tri, ngi
chi 2 xut hin gc di bn phi ca cc bn c sn. Thi gian

ca vn u bt u m ngc ( 200s ).
Mi ngi chi c 4 phm di chuyn:
Player 1
Player 2
M t
Di chuyn sang tri
Di chuyn xung di
Di chuyn sang phi
Di chuyn ln trn
Space
t bom
Hinh 1 Cc phm c s dng chi
an u mi ngi chi ch c mt mng. Sau khi bom n trng

ngi chi, tr chi kt thc .
Mi ln n phm mi ngi ch t c 1 qu v bom t n sau khi

t l 3s
Ngi chi di chuyn vi cc bc i l 1/4 t bom v khng c

i qua bom, gch v .
Gch b ph v khi bom n 1 ln, khng b ph v.
1.3.2.Tnh im.
-
20: Ph gch
Page 6

an u mi ngi chi khng c im no, s im ca mi ngi
s c cp nht trong mi vn v hin th ln mn hnh.
1.3.3.Kt thc.
- Tr chi kt thc khi 1 ngi dnh bom hoc ht thi gian ca 1 vn u
(200s)
- Khi ht gi m khng ai b bom n th s so im. Ai nhiu im hn l
thng
1.4. K hoch thc hin v phn cng cng vic.

1.4.1. K hoch thc hin
Tng thi gian thc hin: 01 thng (27/7/2012 - 28/8/2012)

Bo co hng tun: sng th 7 hng tun, trnh by cc cng vic
hin ti, thc mc cn gii p
Bo co cui cng: Th 7, 1/9/2012, bo co hon chnh v kt thc
ti
Tun 0: 26/7/2012 - 28/7/2012
Hon thnh spec ca game, nh hnh s khi cho c h thng.
Tun 1: 29/7/2012 - 04/7/2012
c ti liu v vit khi iu khin VGA, PS2
Xy dng bn c nh
Bt tn hiu ca nhiu phm
Tun 2: 05/8/2012 - 11/8/2012
Hin th, iu khin nhn vt di chuyn v trnh trn bn .
Page 7

Tun 3: 12/8/2012 - 18/8/2012
t bom, bom n to ra la, ph gch v git c i phng
Xy dng text cho cc mn chi
Tun 4: 19/8/2012 - 25/8/2012
Ghp v hon thin code
Test game, tm li pht sinh v sa
Tun 5: 26/8/2012 - 1/9/2012
Vit bo co hon chnh v trnh by ti.
1.4.2. Phn cng cng vic
Hon thin spec v s khi chung cho c h thng
: C nhm
Hin th VGA, hon thin mn chi chnh, ghp code
: Khnh
Bt phm, hin th text cho cc mn chi, ghp code
: Ngc
Vit bo co cui cng
: C nhm
2. Gii thiu Cng ngh s dng.

2.1. Phn cng.
Kit DE1
DE1 ( Development and Education ) l mt phin bn thu nh ca Kit DE2. N rt
ph h h c in t s, k thut my tnh v FPGAs. Con chip Cyclon II 2C20
trn DE1 c thit k chyn phc v cho mc ch gio dc nh trong cc
phng lab ca cc trng i h c, cao ng. N ph hp lm nhiu bi tp trong
cc mn h c nh in t s, k thut my tnh .. thng qua cc v d n gin.
Page 8

Thng s c bn ca kit DE1:
B nh:
-
8Mb SDRAM.
512Kb SRAM.
4Mb Flash.
m thanh.
-
H tr b codec 24 bit.
Cng tc v ch th.
-
10 cng tc chuyn v 4 nt bm.
4 led 7 thanh.
10 LED v 8 LED xanh.
Cc kt ni
-
VGA, RS-232, v PS2.
2 cng m rng 40 chn.
Khe cm SD/MMC.
Ngun
-
C th ngun t cp USB hoc thng qua cp ngun ring.
Hinh 2 Kit DE 1
Page 9

2.2. Phn mm Quartus II 9.1.
Quartus II l cng c chnh c s dng trong qu trinh thc hin ti.
c cung cp v cp nht thng xuyn bi Altera. y l cng c thit k tt
nht cho cc dng chip FPGA ca Altera bao gm c Cyclon II 2C20 c trn DE1.
L cng c phn tch v tng hp thit k HDL, n cho php nh pht trin
thc hin thit k ca h , ng thi cho php phn tch thi gian, kim tra s
RTL, m phng h thng v cu hnh sn phm mt cch ph hp nht.
2.3. Quy trnh thit k FPGA vi Quartus II.
Di y l quy trnh thit k FPGA vi cc phn mm thit k FPGA ni chung v
Quartus II ni ring:
Hinh 3 Design Flow
Page 10

N bao gm cc bc c bn sau:
Design Entry Mch sau thit k s c m t bi cc ngn ng m t
phn cng nh VHDL hay Verilog, hoc cng c th dng s Schematic.
Synthesis Cng c t hp s t hp mch to ra mt file netlist c cha cc
phn t logic v cc kt ni gia chng.
Function Simulation Chc nng ca mch sau t hp s c kim nh.
Fitting Cng c my tnh s t cc phn t logic c nh ngha trong file
netlist xung cc phn t logic trong con chip FPGA thc t. ng thi ch n ra
cc ng dy kt ni chng vi nhau.
Timming Analysis Phn tch tr truyn dn trn cc ng dy khc nhau
nhm a ra cc ch th gip ci thin hiu nng lm vic ca mch.
Timming Simulation Kim tra ng thi c v mt chc nng ln thi gian
ca mch.
Programming and Configuration Thc hin mch trn con chip vt l bng
cch cu hnh cc phn t logic trn chip v thnh lp cc kt ni cn thit.
3. S khi ca h thng.
CU
FONT
PS2
KEYBOARD
INTERFACE
ROM
VGA
MONITOR
CONTROLER
Hinh 4 S TNG QUAN
Page 11

3.1.Bn phm
Bn phm vi chun giao tip PS2. Giao tip vi khi x l thng qua khi PS2
Interface.
3.2.Mn hnh
Mn hnh c s dng l mn hnh my tnh CRT hoc LCD thng dng c
iu khin thng qua khi VGA Controller.
3.3.ROM
c s dng cha font hin th trong game. L distributed ROM - c trnh
bin dch tng hp t cc phn t logic c sn trong chip.
3.4.Khi x l ( CU )
Khi chu trch nhim iu khin ton b h thng.
4. Cc bc xy dng tng khi ca GAME.

4.1. PS2 Keyboard
iu khin c hng di chuyn ca con rn, nhp mc level bt u
chi hay lu tn nu ngi chi t im s cao chng ta phi s dng mt
keyboard.
Hin nay trn th trng c 2 loi keyboard l keyboard cng usb v keyboard
cng ps2.Trong snake game do nhm thc hin th ps2 keyboard c ch n
s dng .Chng ta s ln lt tm hiu v loi keyboard ny cng nh thit k
cc khi cn thit c th nhn c d liu gi t keyboard mt cch chnh
xc.
4.1.1.Khi nhn d liu PS2
- Giao tip vt l cng PS2:
Hinh 5 Cng PS2
Page 12
Mt cng ps2 c bn chn : chn data ps2d, chn clock ps2c v hai chn ngun l
VCC v ground trong chn ngun VCC c cung cp bi host.
D liu t keyboard ti host c truyn qua chn data mt cch ni tip theo
chun UART.Qu trnh truyn d liu bt u vi 1 bit start ,8 bit d liu ,1 bit
chn l v 1 bit stop
Start Bit
(1 bit)
Data Bits
(8 bits)
Odd Parity Bit

(1 bit)
Stop Bit
(1 bit)
Hinh 6 M t mt khi d liu
Clock ca bn phm th c truyn qua chn ps2c c tn s trong khong t

10Khz ti 16,7 Khz, Tn hiu ps2d phi n nh t nht l 5 us trc v sau sn
ln v xung ca tn hiu ps2c. Ta c th thy c iu ny qua hnh m t v
:
Hinh 7 V tr cc bit trong qua trnh nhn d liu .
Page 13

- Khi nhn d liu PS2:
c th thu li c d liu thay v phi thit k mt b ly mu ta s dung mt
mch d sn xung ca tn hiu ps2c lm im tham kho.u vo ca mch bao
gm tn hiu ps2d v ps2c nhn t keyboard ,tn hiu clock ca host ,mt tn hiu
reset ca h thng v mt tn hiu cho php nhn d liu t bn phm. u ra ca
mch s l 8 bit d liu v mt tn hiu bo hiu rx_done_tick.Tn hiu ny mc
cao sau mi chu k clock.
Ta c s khi ca mch nhn :

rx_en
clk
rst
KEYBOARD
ps2d
ps2c
dout (7 downto 0)
ps2_rx
rx_done_tick
Falling edge
Filter & Falling
Edge ps2c
clk
Hinh 8 S khi mch nhn d liu
S ASM ca khi nhn d liu:
Page 14
Idle
F
Rx_en=1 and
Fail_edge=1
T
b<=ps2d (b>>1)
n<= 9
dps
F
Fail_edge=1
b<= ps2d & (b>>1)
n=0
n<=n-1
T
Load
rx_done_tick <=1
Hinh 9
ASM ca mch nhn
V c bn, mch hot ng nh sau:
Page 15

-
Trc tin trng thi ch, mch s kim tra sn xung ca tn hiu clock
ca PS2 v nhn l start bit.
Sau khi xc nh c start bit mch s nhn vo 10 bit tip theo bao gm 8
bit d liu, 1 bit chn l v 1 bit stop.
Cui cng xut ra 8 bit d liu v chuyn v trng thi ch.
4.1.2.Mch giao tip vi PS2 Keyboard.
Trong mc ny chng ta s i tm hiu v cch m ha bn phm ng thi thit k

mt mch gii m cc lnh gi t bn phm ti Host.
a. Tng quan v m ha bn phm
Mt bn phm l ma trn cc phm.N c nhng mt con vi iu khin iu
cc hot ng ca bn phm.C 3 ch hot ng ca cc phm c th xy ra l :
Khi ta bm mt phm th make code ca phm c truyn
i.
-
Khi ta gi mt phm vi thi gian ln khong 0,5 s th make

code s c truyn i mt cch lp li vi mt tc xc nh chu k 100 ms.
Khi ta nh phm th break code ca phm s c truyn.
Hnh v di y s cho ta thy make code ca cc phm ca keyboard

:
Page 16

Hinh 10 Make code ca cc phm ca keyboard
i vi cc phm thng th make code ca n c kch thc l 1 byte cn i vi

cc
phm m rng th kch thc l t 2 byte cho n 4 byte. PS2 keyboard s
truyn tun t code ty theo hot ng ca phm. V d ta bm v nh phm A th

u tin make code c gi vo sau l break code ca n :
1C F0 1C
i vi phm m rng v d nt up :
E0 75 F0 E0 75
Nu ta nhn mt phm lu sau nh ra th make code s c gi nhiu ln :

1C 1C 1C .. F0 1C
Nu nhiu phm c bm cng mt lc th code gi i ln lt l make code v
break code ca 2 phm.v d ta bm 2 phm Shift v A cng lc th coe gi i s l :
12 1C F0 1C F0 12
b. Mch giao tip PS2 keyboard
Mch giao tip PS2 keyboard lm nhim v l c ly thnh phn chnh trong scan
code thu c sau cc hot ng bm v nh phm.ng thi to ra mt tn hiu
bo hiu b iu khin c th nhn ra c u l phm m rng (thng thng
phc v cho mc ch chuyn ng ca con rn ,ch n level chi) u l phm
thng (dng trong vic lu tn trong trng hp ngi chi t kt qu cao)
C 2 cch thu li thnh phn chnh trong scan code t hot ng nhn nh phm
l bt break code v bt make code.Trong snake game m nhm thc hin th nhm
ch n cch bt make code s chnh xc hn v cc lnh s c thc hin ngay lp
tc ngay sau khi c nhp trnh c khong thi gian tr ch nh phm nu
chng ta dng cch bt break code.
S khi ca mch giao tip vi PS2 keyboard :
Page 17
ps2c
ps2d
ps2c
Key_code
dout
w_data
ps2d
got_tick
done_tick
clk
r_data
wr
rd
got_key
FSM to
get make
code
PS2_rx
Hinh 11
FIFO
giao tip vi PS2 keyboard
im ch trong mch ny l tn hiu got_key.Sau khi mch nhn d liu c gi

t PS2 keyboard cho u ra l dout v mt tn hiu bo hiu l done_tick.tn hiu
u ra ny s c a ti mt mch FSM xc nh thnh phn chnh ca code
m ta cn thu li phc v cho cc mc ch ca chng ta.Tn hiu got_tick s tch
cc cao khi mch FSM xc nh c thnh phn code cn c ,ng thi cho php
ghi thnh phn code ny vo b FiFo ch cho Control Unit x l.
c. s khi giao tip vi PS 2 ( * bt nhiu phm)
Test trn kit De1 vi cc led red v green. Mi led sng (tt) tng ng vi 1
phm c nhn (nh). Phng php: S dng 3 thanh ghi 8 bit .
- Trong b Ps2_check c cha ba thanh ghi 8 bit.
Page 18
Hinh 12 ba thanh ghi 8 bit
- V d: Mun bt phm di chuyn sang tri

Left =1 khi byte0 = x6b
Left =0 khi byte0 = x6b , byte1= xf0 v byte3 = xe0
4.2. Khi VGA.
4.2.1. h a
a.
ii hi
- VGA l vit tt ca video graphic array, l mt chun h a c gii

thiu trong cui nhng nm 1980 t pha I M cng loi my tnh PS/2 .Trong cc
phn sau, chng ta s tho lun v giao din c phn gii 640 x 480 vi 8 mu c
bn ca mn hnh CRT ( cathode ray tube).
- Di y l bng kt hp mu t 3 bit ca VGA:
Xanh (G)
Xanh dng B
Xanh dng
Xanh
en
ng
Page 19

1
1
Hinh 13
1
ng k hp m
ng
i c
b. Cng
- Cng VGA c 5 tn hiu tch cc bao gm cc tn hiu ng b theo phng
ngang v phng d c, h_sync v v_sync v 3 tn hiu hnh nh cho 3 mu , xanh,
xanh dng.
- Hnh nh l mt tn hiu tng t, v b iu khin video s dng mt b
chuyn i DAC chuyn i tn hiu s u ra thnh mc tng t mong mun.
Nu mt tn hiu hnh nh N-bit th tn hiu ny c th c chuyn thnh 2N mc
tng t.
- Trong phn tho lun , chng ta dng tn hiu hnh nh mu 3 bit nn u
ra chng ta s thu c 23=8 mu c bn nh c lit k trong bng trn.
4.2.2.
iu khin video
Mt b iu khin hnh nh to ra cc tn hiu ng b v cc pixel d liu

u ra . S nh sau:
External
data/control
rgb
Pixel
Pixel generation
generation
circuit
circuit
pixel_x
pixel_y
video_on
VGA
monitor
h_sync
v_sync
clock
VGA_sync
VGA_sync
Hinh 14 S khi c
khi n
S bao gm:
Mch ng b, k hiu l VGA_sync.
Mch to pixel Pixel generation circuit.
- Mch VGA_sync to ra cc tn hiu ng b v tn hiu thi gian. Tn hiu
h_sync v v_sync c ni vi cng VGA iu khin ch qut theo phng
-
Page 20

ngang v phng d c ca b iu khin. Pixel_x v pixel_y l u ra ca cc tn
hiu c gii m t b m bn trong. Hai tn hiu ny xc nh v tr ca pixel
hin ti. Mch VGA_sync cng to ra tn hiu video_on xc nh khi no th kch
hot hay v hiu ha tn hiu hin th trn mn hnh.
- Mch pixel generation circuit to ra 3 tn hiu hnh nh rgb. Mu thu c
tng ng vi t a ca cc pixel hin ti v cc tn hiu d liu v iu khin t
bn ngoi.
a.
ch ng
- Mch ny to ra cc tn hiu ng b theo phng ngang h_sync v ng b
theo phng d c v_sync. Trong :
h_sync: ch ra thi gian cn thit qut ht mt hng.
v_sync: ch ra thi gian cn thit qut ht ton b mn hnh.
- Trong phn tho lun ca chng ta dn mn hnh c phn gii 640x480
vi tc pixel l 25Mhz, ngha l trong 1s mn hnh x l 25M pixel.
- Mn hnh bao gm vng vin en xung quanh mn hnh v vng nhn thy
gia c hnh ch nht. Cc trc t a v chiu dng ca cc trc nh hnh v
di y:
x
border
Visible area
y
h_video_on
639 655 751 799
0
h_sync
display
Left
border
Right
border
Hinh 15
S h i gi n q
retrace
Left
border
h o phng ng ng
Page 21

i
- S thi gian qut ca tn hiu ng b theo phng ngang nh hnh 2.

Mt chu k ca tn hiu h_sync c chia lm 4 vng:
Vng hin th: l vng m cc pixel c hin th trn mn hnh.
Vng qut ngc: l vng m cc tia in t quay ngc li v pha
cnh bn tri.
Vng bin phi: l vng mu en bn phi, trong vng ny cc tn
hnh nh b v hiu ha khng c hin th.
Vng bin tri: l vng mu en bn tri v ging nh vng bin bn
phi, trong vng ny th cc tn hiu hnh nh khng c hn th.
i
S thi gian qut ca tn hiu ng b theo phng d c nh sau:
v_video_on
479 489 491 524
0
v_sync
display
Top
border
Top
border
Bottom retrace
border
Hinh 16 S h i gi n c
n hi q
h o phng
Trong :
Vng hin th: l vng m cc pixel c hin th trn mn hnh.
Vng qut ngc: l vng m cc tia in t quay ngc li v pha
cnh bn tri.
Vng bin trn: l vng mu en bn trn, trong vng ny cc tn hnh
nh b v hiu ha khng c hin th.
Vng bin di: l vng mu en bn di v ging nh vng bin
bn trn, trong vng ny th cc tn hiu hnh nh khng c hn th.
-
b.
c pi l
Page 22

- G i p l s pixel trong 1 hng ngang, l l s ng ngang trong 1 mn hnh
v s l s mn hnh hin th trong 1 s th tc pixel bng p*l*s.
h
n h nh h ng nh p nh th s ph i ln hn ho c ng 2
- Vi mn hnh c phn gii 640x480 v s mn hnh hin th trong 1s l 60
h nh s th p = 800 pixel/line, l=525 line/screen, s=60 screen/second tc pixel
bng 800x525x60 25M pixel/s.
c.
ch o pi l
- Mch to pixel to ra tn hiu mu 3 bit rgb cho cng VGA. Tn hiu iu

khin v d liu t bn ngoi ch ra ni dung cn hin th trn mn hnh, pixel_x v
pixel_y ch ra t a hin ti ca pixel. C 3 loi mch to pixel:
S kiu bit mapped .
S kiu tile mapped .
S kiu object mapped.
- Trong s kiu bit mapped, d liu hin th trn mn hnh c lu tr
trong mt b nh. Mi pixel c lu tr trc tip trong b nh to thnh t nh (
memory word )v tn hiu pixel_x, pixel_y to ra a ch ca nh. Mt mch x l
h a lin tc cp nht mn hnh v ghi d liu vo nh. Mt mch thu lin tc
c t b nh v truyn d liu ti tn hiu rgb. S bit mapped thng c
dng to mu. Nhc im khi s dng s ny l tn b nh.
- gim yu cu b nh, ngi ta dng s kiu tile mapped . Trong s
kiu ny, chng ta nhm mt tp bit to thnh 1 tile ( gch ) v coi mi tile
nh 1 bit. S ny thng c dng to text.
- Cui cung, s kiu object mapped thng c dng to ra cc vt
th. Trong cc bo ton, chng ta thng kt hp c 3 cch trn to ra mt mn
hnh hon chnh.
S ki
o j c mapped .
Page 23

Data/control
Video_on
pixel_x
pixel_y
rgb
mux
Object
Object 11
Generation
Generation circuit
circuit
Object
Object 22
Generation
Generation circuit
circuit
Object
Object 33
Generation
Generation circuit
circuit
Hinh 17 S khi c mch o j c mapped
- S khi bao gm cc mch to ra cc vt th, mt b mux ch n vt th

hin th. Mch ny thc hin cc chc nng sau:
Gi t a ca cc vt th v so snh cc t a ny vi v tr hin ti
m pixel_x v pixel_y cung cp.
Nu v tr hin ti ca vt th trong vng hin th th mch ny s
ch n thm tn hiu on ca vt th .
Ch ra tn hiu mu ca vt th.
mux kim tra cc tn hiu on v xc nh tn no c truyn ti tn hiu
u ra rgb.
i u it mapped
Trong kiu s ny, mi pixel to thnh 1 nh nn nhc im ca phng
php ny l rt tn b nh. Cch tip cn ny khng yu cu thm mch chuyn
cc tn hiu pixel_ x v pixel_y thnh a ch nh nhng lng ph nhiu b nh.
i u tile mapped
S kiu ny c dng to text v s c tho lun trong sau.
Page 24
rgb

4.2.3. VGA text.
a.
ii hi
- S kiu tile mapped c dng to text v cc k t . Mi tile c

coi nh mt siu pixel . Phng php xy dng cc k t l coi chng nh cc tile
v thit k mch to pixel bng phng php ny.
b. o
- Khi p dng phng php ny, mi k t c coi nh mt tile, gi tr ca
mt tile biu din m ca mt v mu c th. Chng ta s dng m ASCII 7 bit
cho cc k t.
- Mu ca cc tile to nn font ch ca tp cc k t. C nhiu loi font ch
nhng trong phn tho lun ca chng ta dng font ch c kch thc 8x16( 8 ct v
16 hng ).
00000000
00000000
00000000
00000000
00010000
00010000
00111000
00111000
01101100
01101100
11000110
11000110
11000110
11000110
11111110
11111110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
11000110
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Hinh 18
on c k
- Cc k t bao gm phn s, cc ch ci hoa v ch ci thng, cc biu

tng v nhiu k t h a c bit.
- i vi mn hnh c phn gii 640 x480 , khi s dng cc tile c kch
thc 8 x16 th mi hng ngang cha va 80 tile v mi hng d c cha va 30
tile. Khi ta c th coi mn hnh c phn gii l 80 x 30.
Page 25

d. Font ROM
- thc hin cc k t m ASCII, chng ta s dng font ROM . Gi s chng
ta thc hin 128 k t u ca bng m ASCII th kch thc ca ROM l 211 x 8.
Trong , 7 bit c tr ng s cao nht ca 11 bit a ch c dng xc nh k t,
4 bit c tr ng s nh nht c dng xc nh hng trong mt mu ca k t.
Hnh 5 l a ch v ni dung ROM ca k t A.
- Cch thc hin nh sau:
constant ADDR_WIDTH: integer :=ll;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector (ADDR_WIDTH -1 downto
0);
type rom_type is array (0 to 2**ADDR_WIDTH-l)
-- ROM definition
constant RUM: rom_type :=
-- code
x00
(blank space)
00000000, -- 0
00000000, -- 1
00000000, -- 2
00000000, -- 3
00000000, -- 4
00000000, -- 5
00000000, -- 6
00000000, -- 7
00000000, -- 8
00000000, -- 9
00000000, -- a
00000000, -- b
00000000, -- c
00000000, -- d
00000000, -- e
00000000, -- f
...
begin
-- addr register to infer block RAM
Page 26

process (clk)
begin
if (clkevent and clk = 1) then addr-reg
end
if ;
end
process;
data
end
e.
<=
addr;
<= ROM(to_integer(unsigned(addr_reg))) ;
arch;
ch o
c n
- Mch to pixel to ra cc gi tr ca pixel tng ng vi t a ca pixel

hin ti v cc tn hiu d liu/iu khin bn ngoi. Mch to pixel da trn s
kiu tile mapped lin quan ti 2 giai on. giai on th nht dng cc bit cao
ca pixel_x v pixel_y to ra m ca mt tile, v giai on th hai dng m ny
v cc bit thp to ra gi tr ca pixel.
- Theo phng php ny th mn hnh c coi nh c phn gii 80x30 tile,
mi tile l mt c kch thc 8x16. u tin, pixel x v pixel s ch ra t a
ca v tr tile hin ti. Mch to k t s dng nhng t a ny kt hp vi cc tn
hiu d liu/ iu khin t bn ngoi to ra gi tr ca tlie tng ng vi m
ASCII. Tip theo, m ASCII ny s lm 7 bit cao ca a ch ca font ROM v ch
ra v tr ca mu ang xt. Kt hp vi 4 bit thp ca t a y hnh thnh nn a
ch y ca font ROM. u ra ca font ROM tng ng vi 8 bit hng ngang
ca mt mu, cn 3 bit c tr ng s nh nht ca t a x ch ra v tr ca pixel.
f.
l c on
- Trong s kiu tile mapped chng ta c th iu chnh kch thc ca
cc pixel. Chng hn, chng ta c th m rng t font c kch thc 8x16 ln font
c kch thc 16x32. thc hin c cng vic ny, chng ta ch cn dch phi
t a ca pixel 1 bit v b i bit c tr ng s nh nht ca pixel_x v pixel_y.
Page 27

4.3. Khi di chuyn.
Hinh 19 S THUT TON KHI DI CHUYN
an u, 2 nhn vt xut hin 2 gc mn hnh cho nhau. Khi phm di

chuyn c nhn, ta s xt xem t a tip theo m nhn vt di chuyn ti c l
hay gch khng. Nu khng th gn bin move_step<= 8 ( bc di chuyn ca nhn
vt), nu c th gn bin move_step<= 0. Sau ta lu t a mi ca nhn vt,
ng thi nh du hng di chuyn ca nhn vt phc v qu trnh t bom sau
ny.
Page 28

4.4 Khi t bom.
Hinh 20 S I THUT TON KHI T BOM
Khi c tn hiu t bom, ta s lu li t a nhn vt khi t bom chnh li

v tr t bom u tin theo hng di chuyn ( V d: khi nhn vt ang sang ph i th
ta bom l : bom (x,y) = nhan_vat (x-1,y) ), ng thi b counter bt u m ,
v gn bin bomb_set = 1( hi n th bom ) . n khi counter m n gi tr t
trc, ta gn o
set = 0 v fire set = 1( Th i hi n th bom m hi n th la ).
Page 29

Ph gch :
T t a t bom , khi c tn hiu hin th la fire on=1,
ta gn cc phn t m ng vi cc t a lin k ca bom ca mng
Brick bng 0 .
Nhn vt mt mng:
Khi qut mn hnh m thy t a nhn vt trng vi t a la th
nhn vt s b mt mng.
4.5. Khi hin th TEXT
Hinh 21 TEXT CONTROL
Khi iu khin text vi u vo gm cc tn hiu pixel_x v pixel_y xc nh v

tr pixel ang c qut trn mn hnh. Cc tn hiu key_up, key_down di
chuyn ln hoc xung xc nh text ang c ch n. Tn hiu SW iu khin cc
text hin th trong tng mn hnh. Tn hiu ra s c a qua b mux la ch n
text hin th ln mn hnh kt hp vi cc tn hiu ng b v_sync v h_sync
Page 30

Mn hnh u vo:
Hinh 22
START GAME
Hinh 23 S RTL KHI TEXT
Page 31

-
S dng font mu: 8x8 pixel
Cc font c kch thc ln hn c th m rng t font mu
VD: Text OM ERMAN l 64x64 font thu c bng cch dch t a

pixel_x v pixel_y sang phi 3 bit
4.6 Khi counter
Page 32

Hnh 24: S khi counter
Khi counter thc hin vic m ngc t 200s -> 0 xc nh thi gian ca
ngi chi cho mt vn u. Tn hiu timer_tick s dng tick 60 Hz . Khi
timer_start c xc nh b m bt u hot ng. Khi b m n 0 th tn hiu
timer_up c xc nh lm tn hiu chuyn mn chi.
4.7 S FSM ca game

Reset
Key = 0
New Game
Key = 1
Over = 0
Play
Key = 1
Over = 1
Game Over
S S
c g m
Page 33

Hnh 25. S FSM ca game
C 3 trng thi chnh l New Game, Play v Game Over. Cc tc nhn gy ra dch
chuyn trng thi l tn hiu Key v Over
C. KT LUN
1. Kt qu t c.
Game thu c st vi spec ra
Giao din cn n gin, cc chc nng cn s si
Cha c vt phm
2. Kh khn.
V thi gian cn hn ch v li ri vo thi im thi h c k h nn chng
em mi ch hon thin c cc chc nng c bn nht.
K nng c ti liu ting anh cn hn ch nn mt kh nhiu thi gian
Vic chia s dng kit gp kh khn v cc thnh vin kh xa nhau.
3. Xut.
-
Ghp thm phn AUDIO cho Game sinh ng hn.
Page 34
Ph lc
Hinh 1 Cc phm c s dng chi ..........................................................................6
Hinh 2 Kit DE 1 ..........................................................................................................9
Hinh 3 Design Flow .................................................................................................10
Hinh 4 S TNG QUAN ..................................................................................11
Hinh 5 Cng PS2 .......................................................................................................12
Hinh 6 M t mt khi d liu ..................................................................................13
Hinh 7 V tr cc bit trong qua trnh nhn d liu . ...................................................13
Hinh 8 S khi mch nhn d liu ......................................................................14
Hinh 9
ASM ca mch nhn .................................................................................15
Hinh 10 Make code ca cc phm ca keyboard .....................................................17

Hinh 11
giao tip vi PS2 keyboard ......................................................................18
Hinh 12 ba thanh ghi 8 bit ........................................................................................19

Hinh 13 bng kt hp mu t 3 bit ca VGA ..........................................................20
Hinh 14
S khi ca b iu khin VGA .........................................................20
Hinh 15
S thi gian qut theo phng ngang .................................................21
Hinh 16 S thi gian ca tn hiu qut theo phng d c....................................22

Hinh 17 S khi ca mch object mapped.......................................................24
Hinh 18 Mu k t v font ca k t .........................................................................25
Hinh 19 S THUT TON KHI DI CHUYN ............................................28
Hinh 20 S I THUT TON KHI T BOM .............................................29
Hinh 21 TEXT CONTROL .....................................................................................30
Hinh 22
START GAME ........................................................................................31
Hinh 23 S RTL KHI TEXT ........................................................................31

Page 35
Ti liu tham kho
[1] FPGA Prototyping VHDL Examples - Xilinx Spartan-3 version . PONG P.CHU.
[2] Rapid.Prototyping.of.Digital.Systems
[3] MIT Press - Circuit Design with VHDL (2007)
[4] http://esrc618.wordpress.com/
[5] http://vuhuutiep.wordpress.com/
[6] http://www.dientuvietnam.net/forums/gal-pal-cpld-fpga-59/tam-su-ve-fpga33377/
Page 36

Bao Cao Game Fix

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Final Report Bomberman Game on DE1 board

HA NOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

VHDL TRAINING COURSE

Ha Noi, July 27, 2012

Final Report Bomberman Game on DE1 board

1.Tng Quan ti. ....................................................................................................5

Final Report Bomberman Game on DE1 board

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

chi 2 xut hin gc di bn phi ca cc bn c sn. Thi gian

Di chuyn sang tri

Di chuyn sang phi

Hinh 1 Cc phm c s dng chi

an u mi ngi chi ch c mt mng. Sau khi bom n trng

Mi ln n phm mi ngi ch t c 1 qu v bom t n sau khi

Ngi chi di chuyn vi cc bc i l 1/4 t bom v khng c

Gch b ph v khi bom n 1 ln, khng b ph v.

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

1.4. K hoch thc hin v phn cng cng vic.

Tng thi gian thc hin: 01 thng (27/7/2012 - 28/8/2012)

Final Report Bomberman Game on DE1 board

Hin th VGA, hon thin mn chi chnh, ghp code

Bt phm, hin th text cho cc mn chi, ghp code

Vit bo co cui cng

2. Gii thiu Cng ngh s dng.

Final Report Bomberman Game on DE1 board

10 cng tc chuyn v 4 nt bm.

10 LED v 8 LED xanh.

VGA, RS-232, v PS2.

2 cng m rng 40 chn.

C th ngun t cp USB hoc thng qua cp ngun ring.

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Hinh 3 Design Flow

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Hinh 4 S TNG QUAN

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

4. Cc bc xy dng tng khi ca GAME.

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Odd Parity Bit

Hinh 6 M t mt khi d liu

Clock ca bn phm th c truyn qua chn ps2c c tn s trong khong t

Hinh 7 V tr cc bit trong qua trnh nhn d liu .

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Ta c s khi ca mch nhn :

Hinh 8 S khi mch nhn d liu

S ASM ca khi nhn d liu:

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

b<= ps2d & (b>>1)

ASM ca mch nhn

V c bn, mch hot ng nh sau:

Group 1- K54 ESRC LAB

Final Report Bomberman Game on DE1 board

Cui cng xut ra 8 bit d liu v chuyn v trng thi ch.