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P. 1
COMPARISON OF NEUTRON, PROTON AND GAMMA RAY EFFECTS IN SEMICONDUCTOR DEVICES

COMPARISON OF NEUTRON, PROTON AND GAMMA RAY EFFECTS IN SEMICONDUCTOR DEVICES

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Published by Jimmy Fallony
Interest in proton radiation effects has
intensified in recent years. A prime focus is the relationship between proton displacement and ionization effects and the separate consideration of neutron-induced displacement and gamma-ionization
effects in TREE characterization. Recent definitive work on proton and neutron displacement damage in silicon in terms of nonionizing energy loss has laid the groundwork for comparison of proton effects with the TREE data base. We initiate this comparison with a summary of device radiation susceptibilities in neutron and gamma environments. Proton interactions
in silicon devices are then presented in terms of dose deposition and nonionizing energy loss. This leads to a neutron-proton damage equivalence factor and enables the development of simple correspondence.
The device susceptibility charts are then combined so
both displacement damage and ionization-damage can be schematically examined relative to proton dose. These susceptibility charts demonstrate the dominance of ionization effects for damage in a proton environment for modern silicon microcircuit technologies. This approach is presented as a convenient means of interpreting effects for both proton exposures and TREE simulators. It is concluded that TREE characterization can be used as a good first-order estimate of proton damage effects.
Interest in proton radiation effects has
intensified in recent years. A prime focus is the relationship between proton displacement and ionization effects and the separate consideration of neutron-induced displacement and gamma-ionization
effects in TREE characterization. Recent definitive work on proton and neutron displacement damage in silicon in terms of nonionizing energy loss has laid the groundwork for comparison of proton effects with the TREE data base. We initiate this comparison with a summary of device radiation susceptibilities in neutron and gamma environments. Proton interactions
in silicon devices are then presented in terms of dose deposition and nonionizing energy loss. This leads to a neutron-proton damage equivalence factor and enables the development of simple correspondence.
The device susceptibility charts are then combined so
both displacement damage and ionization-damage can be schematically examined relative to proton dose. These susceptibility charts demonstrate the dominance of ionization effects for damage in a proton environment for modern silicon microcircuit technologies. This approach is presented as a convenient means of interpreting effects for both proton exposures and TREE simulators. It is concluded that TREE characterization can be used as a good first-order estimate of proton damage effects.

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Published by: Jimmy Fallony on Feb 03, 2013
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1621
SESSION
J:
RADIATION
EFFECTS
AND
DEVICES
 
IEEE
Transactions
on
Nuclear
Science,
Vol.
NS-34,
No.
6,
December
1987
COMPARISON
OF
NEUTRON,
PROTONANDGAMMA
RAY
EFFECTS
IN
SEMICONDUCTOR
DEVICES*
J.P.
Raymond
Mission
Research
Corporation
San
Diego,CA
E.L.
Petersen
Naval
ResearchLaboratory
Washington,
DC
ABSTRACTInterest
in
protonradiationeffects
has
intensified
in
recent
years.
A
primefocus
is
the
relationship
between
proton
displacement
andioniza-tion
effects
and
the
separate
consideration
of
neutron-induceddisplacement
and
gamma-ionizationeffects
in
TREE
characterization.
Recent
definitive
work
on
proton
and
neutron
displacement
damage
in
silicon
in
terms
of
nonionizing
energy
loss
haslaidthe
groundwork
for
comparisonof
proton
effectswith
theTREE
data
base.
We
initiate
this
comparison
with
a
summary
ofdeviceradiation
susceptibilities
in
neutron
and
gamma
environments.
Proton
interactions
in
silicondevices
arethen
presented
in
termsof
dose
deposition
and
nonionizing
energy
loss.
This
leads
to
a
neutron-protondamage
equivalence
factor
and
enables
the
development
of
simple
correspondence.
Thedevicesusceptibilitycharts
are
then
combined
so
bothdisplacement
damageand
ionization-damage
can
be
schematically
examinedrelative
to
proton
dose.These
susceptibility
chartsdemonstratethe
dominance
of
ionization
effects
for
damage
in
a
proton
environ-
ment
for
modernsilicon
microcircuittechnologies.
This
approach
is
presented
as
a
convenient
meansof
interpreting
effects
for
both
protonexposuresandTREE
simulators.
It
is
concludedthat
TREE
characte-
rization
can
be
used
as
a
goodfirst-orderestimate
ofproton
damage
effects.
1.
INTRODUCTION
In
the
assessment
of
proton-induced
damage
to
silicon
microcircuits,
it
would
be
veryuseful
to
draw
from
the
knowledge
gained
from
the
study
of
transientradiationeffects
on
electronics
(TREE)
overthe
last
25
years.
Extensive
facilities
have
been
built
to
enable
the
assessment
of
performance
degradation
effects
in
semiconductor
devices
result-
ing
from
neutron-inducedatomic
displacements
and
gamma-ray-induced
ionization.
The
existing
TREEdata
base
would
be
applicable
to
protoneffects
assess-
ment,
given
correlation
of
displacement
damage
and
ionization
effects.
In
addition,
given
correlation,
the
number
of
facilities
available
for
proton
damage
assessment
can
be
expanded
to
include
theTREE
simu-
lation
facilities
as
well
as
available
cyclotrons.
Correlation
of
proton
damage
effects
to
both
neutron
displacement
damage
and
ionizing
radia-
tion
exposure
has
been
established
by
a
number
of
basicmaterial
anddevice
studies
[1-4].
In
this
paper
the
correlation
willbe
interpreted
in
terms
of
device
TREE
susceptibility.
This
interpretation
clearly
indicates
that
long-term
ionization
effects
are
the
primarydamage
mechanism
for
proton
exposure
of
virtually
all
types
of
modern
silicon
microcir-
cuits.
2.
DEVICE
SUSCEPTILBIITYASSESSMENT
Characterization
of
displacement
and
long-
term
ionizationdamageeffects
on
semiconductor
piece-parts
is
routine
in
the
supportofthe
development
ofsystems
whichmust
behardened
to
nuclearweapon
andspace
radiationenvironments.
Typically,
it
is
assumedthat
the
displacement
damage
and
ionizationeffects
are
independent,
so
that
damagecharacteriza-
tionscanbe
done
separately.Thefacilitiesused
to
characterize
TREEare
a
pulsednuclear
reactor
for
the
neutron
source,and
a
Cobalt-60source
or
electronaccelerator
(e.g.,
Dynamitrons,
linear
accelerators,
Van
de
Graaffgenerators)
for
theionizationsource.
2.1
Neutron
Displacement
DamageTheexposure
environment
of
a
pulsednuclear
reactor
includes
high-energy
neutronsandconcomitant
gamma
rays.A
comprehensive
characterization
ofsemi-
conductordeviceeffects
includes
the
timedependentnatureofneutron
displacement
damage
and
ionization
as
potential
failuremechanisms.
The
device(s)
undertest
would
be
activelybiased
during
exposure,thetest
conditionswould
be
carefullyselected,
and
the
response(s)
would
be
monitored
during
and
after
expo-
sure.
Fortunately,
however,ifonlycharacterizationofstableneutron
displacement
damageeffects
is
of
interestthere
is
virtually
no
dependenceof
the
result
on
thetest
conditions
duringexposure,
and
devices
are
routinely
exposedwith
no
electrical
con-
nection
(usually
with
all
external
leads
shorted
in
conductive
foam).
In
termsofthe
radiationeffects
database,neutron
damagesusceptabil
ity
is
most
frequently
reported
in
terms
ofneutron
fluence
atthe
failure
level
observed
after
a
series
of
reactor
exposures.
Results
of
these
characterizations
can
be
summarized
as
a
range
ofdevice
susceptibility
for
major
micro-
circuit
technologies
as
shown
in
Figure
1.
Neutron
failurelevels
for
the
MOS
technologies
are
estimated
basedonly
on
displacement
damage
effects.
The
firstorder
effect
in
n-MOS
technologies
is
the
degradation
of
minority
carrier
lifetime,
whichincreases
critical
leakage
currents
in
high-performance
arrays.The
estimate
of
critical
displacementdamage
effects
in
bulk
CMOS
is
based
on
reported
limitations
in
the
use
of
neutron
exposure
to
reducelifetime
and
increase
latchup
hardness
[5,6].
The
estimate
ofcritical
dis-
placementdamage
effects
on
CMOS/SOS
microcircuits
is
based
on
relativelyearly
evaluations.
In
recent
years
it
has
been
assumed
that
the
hardness
is
domi-
natedby
ionization-induced
damage
[7].
Neutron
failurelevels
for
bipolar
microcir-
cuit
technology
reflect
the
sensitivity
ofcircuit
performance
to
the
dominant
degradation
in
transistor
common-emittergain,
as
well
as
the
evolution
to*Work
was
partially
sponsored
by
the
LTH-4.2
Program
through
Naval
Research
Laboratory
Contract
N00014-85-C-2642.
0018-9499/87/1200-1622$01.00
C
1987
IEEE
1622
 
1623
transistors
with
higher
gain-bandwidth
products
and
thuslowerneutrondamage
susceptibility
[8].
The
failurelevels
for
theTTL
microcircuits
reflect
relatively
old
gold-doped
devices
in
which
minoritycarrier
lifetime
degradation
is
notcritical.The
evolution
to
non-gold-doped
Low-Power
TTL
results
in
greater
sensitivity
to
minority
carrierlifetime
degradation
and
an
increasingdependence
on
relative-
lyhigh
transistorgains
with
advances
in
processing
control.The
high
neutron
failurelevels
ofboth
Junction-Isolated
ECL
and
all
oxide-separated
bipolar
digital
circuit
technologiesreflects
the
application
of
very
high
gain-bandwidth
transistor
elements.The
neutron
susceptibility
ofECL
is
slightly
reduced
because
ofthetrend
to
depend
on
relatively
high
transistor
gains.
The
neutron
susceptibility
of
ana-
logbipolar
is
shown
as
a
very
broad
rangebecause
the
failure
level
reflects
both
a
substantial
varia-
tion
in
process
technology
and
depends
critically
on
thedemandsof
the
performancerequirements.
The
failure
level
for
a
very
precise,
high
performance
analogdevice
will
be
muchless
than
that
of
the
analog
device
in
an
applicaiton
thatallows
substan-
tial
degradation
of
the
performance
parameters.
The
estimated
rangesof
microcircuit
neu-
tron
damage
susceptibility
are
shown
in
the
tradi-
tional
barchart
form
in
Figure
1
(Refs.
8,
9).
The
specific
ranges
ofthe
estimated
susceptability
may
be,
and
typically
are,
the
source
of
significant
debate.However,
our
purpose
is
to
focus
attention
on
therangesof
susceptibility
ratherthan
legislate
specificboundaries.
11
121010
TECHNOLOGY
7
2
47
2
n-MOS
Bulk
Si-Gate
CMOS
CommercialHardenedSi-Gate
CMOS/SOS
Commercial
Hardened
Junction-Isolated
Bipolar
TTL
Low-Power
TTL
ECL
Oxide-Separated
Analog
Bipolar
13
14
15
10
1010
4
7
24
72
4
7
2
16
104
7
Bipolar
24
7
2
47
2
4
7
2
4
7
24
7011
1012
1013
1014
1015
10
Neutron
Fluence,
n/cm2,
1
MeV
equivalent
Figure
1.
Estimating
ranges
of
microcircuit
neutron
damagesusceptibility.
2.2
Long-term
IonizationDamage
The
characterization
of
long-term
ionization
damage
is
typicallyperformed
by
exposure
to
gamma
rays
from
a
Cobalt-60
source
or
high
energy
electrons
from
an
accelerator.The
complexities
of
determining
the
system-dependentfailure
level
of
a
given
device
are
legion.
Theyinclude
strong
dependence
on
the
electricalbias
conditionsduring
exposure,
theradi-
ation
intensityduring
exposure,
the
gamma
ray/elec-
tron
energy
spectrum
atthe
device,
electrical
bias
after
exposure,
and
measurement
time
after
exposure.
Currently,
the
techniques
and
facilities
for
exposing
devices
andmeasuring
a
failure
level
in
the
labora-tory
environments
are
well
known.
Unfortunately,
it
is
oftendifficult
to
apply
the
laboratorysimulationfailure
data
to
determine
the
deviceoperationalfailurelevel.
In
this
paper
we
will
considerthe
TREE
database
as
it
exists
in
terms
ofreported
failure
levels
for
laboratory
exposures.
2.2.1
Cobalt-60
ExposureExposure
of
a
semiconductordevice
to
thegammaraysfrom
a
Cobalt-60
sourceis
a
popular
and
relatively
inexpensivemethod
of
determining
ionizing
radiationdamagesusceptibility.Typically,
the
devices
undertest
are
electrically
biased
and
are
eithermonitoredduringexposure
(i.e.,
in
situ)
or
characterized
by
removal
from
thecell
at
definedintervals.
The
reported
failure
levelfor
thedevice
is
generally
reported
in
rads(Si),which
is
inter-
preted
as
essentially
equal
to
the
energy
deposition
by
ionization
in
the
silicon-dioxide
gate
insulator
and
surface
passivation
regions.Gamma
ray
exposure
does
producedisplacmentdamage
in
the
bulksemicon-
ductorthrough
the
resultantCompton
electrons.For
all
practical
purposes,
in
modern
semiconductor
devicesthe
gamma
ray-induceddisplacment
damage
effects
are
negligible
compared
to
the
long-term-
ionization
effects.
2.2.2
High-Energy
Electron
Exposure
High-energyelectron
exposure
is
a
very
popular
approach,
alsousedfor
simulation
of
the
electronexposure
ofthenatural
spaceenvironment.The
facilities
usedfor
simulation
are
principally
Dynamitrons.
A
major
source
of
radiationeffectsdata
is
the
JPL
Voyager/Galileo
Data
Bank
that
includes
results
ofboth
electron
and
Cobalt-60
gammaexposure
[10,11].
Failure
levels
resulting
fromthe
electronexposure
are
reported
either
in
terms
ofrads(Si)
or
electrons/cm2.
In
the
JPL
data
a
conver-
sion
factor
of
4
x
107
e/cm2
per
rad(Si)
is
used
for
the
2
MeV
electron
exposureofthe
Dynamitron
faci-
l
ity.
It
should
be
notedthat
high-energy
photonelectronexposure
cancause
displacementdamage
thatmay
be
important
for
very
sensitive
devices
such
as
some
bipolar
analog
microcircuits.
2.2.3Reported
Ranges
of
DeviceSusceptibilityThefailure
levelsobserved
in
Cobalt-60
and
high-energy
electron
environments
can
be
present-
ed
as
ranges
of
susceptibility
by
technology
as
shown
in
Figure
2
[8,
10-14].
In
addition
to
all
the
caveats
noted
in
the
discussion
ofneutron
failure
levelsummaries,the
long-term-ionization
ranges
must
include
the
significantvariation
of
failure
with
6
bias/time
conditions
andthe
variation
between
high-
performancecommercial
technologies
andradiation-
hardenedtechnologies.The
lowerlimit
on
long-term
ionization
hardness
is
for
high-performance
n-MOS
microcircuits
and
is
on
the
the
order
of
1
krad(Si).
The
hardness
of
commercial
CMOS
is
significantly
greaterthanthat
of
n-MOS
because
of
the
increased
toleranceof
CMOS
circuits
to
radiation-inducedthreshold
voltage
shifts.
The
distinction
between
high-performance
commercialand
hardened
CMOS
is
in
variations
of
fabrication
processes,processcontrol,
and
circuit
design
which,
in
total,
can
increase
the
hardness
by
two
orders
of
magnitude
or
greater.The
hardness
of
commercial
CMOS/SOS
is
somewhat
less
than
that
of
bulkCMOS
because
ofcharge
trapping
effects
atthe
additional
oxide-semiconductor
interfaces.
Again,
hardened
CMOS/SOS
is
distinguished
by
process
and
circuitdesigntechniques
for
hardness
andhard-ness
assurance
even
perhaps
atsome
performance
pen-
alty.
Formanyyears
ithad
been
reasonable
toassume
that
the
long-term-ionization
hardnessof
digitalbipolartechnologies
was
very
high
and
there-
fore
of
little
concern.Thatposition
is
reasonable
for
relatively
highly-doped
junction-isolated
digital

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