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group8_trafficlight

# group8_trafficlight

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02/03/2013

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DaNang university of technology
***************
EE 271 LAB 3(trafficlight)
Group 8
MemberPham Thi TrangOng Thi Hoang AnhDuong Viet Le Ngoc Tan*************DaNang 2012************

Lab 3 Part 1: Traffic light
Block DiagramCode:
//creates slowly clock signalmodule clock_design (clk, clk_out, clr);input clk, clr;output clk_out;parameter which_clock = 1;reg [31:0] divided_clocks = 0;always @(posedge clk or posedge clr)if (clr)divided_clocks=0;elsedivided_clocks = divided_clocks + 1;assign clk_out = divided_clocks[which_clock];endmodule // checking X and delayFlag. If delayFlag=1, set state for outputmodule sensor(out,delayFlag,X,clr);output reg [5:0] out;input X,clr,delayFlag;reg [1:0] state;parameter [1:0] S0=2'd0, S1 = 2'd1, S2=2'd2, S3=2'd3;always@(posedge delayFlag or posedge clr)beginif(clr)

beginstate = S0;out = 6'b100001;endelse if(delayFlag)begincase(state)S0:if(X)beginstate = S1;out = 6'b010001;endS1:beginstate = S2;out = 6'b001100;endS2:if(X==0)beginstate = S3;out = 6'b001010;endS3:beginstate = S0;out = 6'b100001;enddefault:beginstate = S0;out = 6'b100001;endendcaseendendendmodule // sets the time for delaying among above statesmodule set_time(out, delayTime, X, clr);output reg [3:0] delayTime;input [5:0] out;input X, clr;always@(out)beginif(clr)delayTime=0;elsebegin

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