Lecture-wise Breakup

Subject Code Subject Name Credits Faculty (Names) 10B11EC612 Semester Even VLSI TECHNOLOGY AND APPLICATIONS 4 Coordinator(s) Teacher(s) (Alphabetically) Contact Hours 1. Saurabh Chaturvedi 1. Atul Kr. Srivastava 4 2. Mudassar Meer 2. Satyendra Kumar No. of Lectures 3 Semester Even Session 2012-13 Month from January to June

Detailed Syllabii

Module No. 1.

Subtitle of the Module Introduction to VLSI

Topics in the Module Historical Perspective,Overview of VLSI design methodologies, VLSI design flow, Design hierarchy, VLSI design styles MOS structure and operation, MOSFET I-V characteristics, Scaling and small-geometry effects, MOSFET capacitances, MOSFET models for circuit simulation Fabrication process flow, CMOS n-well process, Twin tub process Static and switching characteristics, Delaytime definitions, calculation of delay times, Inverter design with delay constraints CMOS logic circuits, Complex logic circuits, Pass transistor logic, CMOS transmission gates, Sequential logic circuits, Dynamic logic circuits, Stick diagram, Layout, Layout design rules and DRC Language fundamentals, Different modeling techniques using Verilog-HDL DRAM, SRAM, ROM Evolution, application, implementation, programming technology Total number of Lectures

2.

MOS transistor theory

3. 4.

Fabrication of MOSFETs MOS inverters

3 6

5.

MOS logic circuits

12

6. 7. 8.

System specification using HDL Semiconductor memories FPGA and CPLD

5 4 2 43

Recommended Reading material: Author(s), Title, Edition, Publisher, Year of Publication etc. ( Text books, Reference Books, Journals, Reports, Websites etc. in the IEEE format) 1. 2. 3. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3rd Edition, Tata McGraw-Hill Publication, 2003. J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Edition, Pearson Education Inc., 2003. Neil Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective,

4.

3rd Edition, Addison Wesley, 2005. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education Inc., 2nd Edition, 2004.

Evaluation Scheme --1) T1 --- 15 Marks 2) T2 --- 25 Marks 3) T3 --- 35 Marks 4) Teachers Assessment --- 25 Marks -----------------------------------Total Marks = 100 --------------------------------------