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In order to use Pspice for power electronic systems, we have to:
Know background of SPICE Understand Power Electronics Circuits/Systems Know how to use VPULSE to generate useful waveforms Know how to make simple models using ABM
Scope
This presentation covers:
PSpice System/Circuit Level Simulation Power Electronic Circuits/Systems Simulation
SPICE/PSpice
Did you know?
SPICE turns 38 years old this year I Knew SPICE when she was 17 years old I love PSpice because she can do almost anything I need with FOC. I like to talk about her.
Why simulation?
Simulations are essential ingredients of the analysis and design process in power electronics:
Saving of development time Saving of costs (burnt power circuits tend to be expensive) Better understanding of the function
continued
Testing and finding of critical states and regions of operation (Worst Case Analysis) Stress test (Smoke Analysis) Optimization of system Testing new ideas
Overview
Simulation of analog circuits normally uses three basic tools:
SPICE simulator, Mathematical analysis package, and Microsoft Excel.
SPICE
Simulation Program for Integrated Circuit Emphasis Intended for ICs, not for power electronics.
SPICE LIMITATIONS
The Newton-Raphson algorithm is guaranteed to converge if the equations is continuous. The transient analysis has the additional possibility of unable to converge because of the discontinuity in time.
SPICE LIMITATIONS
Computer Hardware Limitation:
Voltage and currents are limited to +/-1e10. Derivatives in PSpice are limited to 1e14. The arithmetic used in PSpice is double precision and has 15 digits of accuracy.
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11
12
Acceptable Bump
Whole car shakes when I hit a bump on the road PSpice doesnt like discontinuity as we dont like a bump on the road.
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Avoid Discontinuity
S G
VGS
VGS
All signals must be made less discontinuous All relationships must be continuous
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15
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V2
PW
V1
TD PER
VPULSE
To Generate Pulse Waveform
Very small values for TR and TF Duty cycle = PW/PER
PW
V2
V1
TR 0
TF 0
PER
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V2 V3 20 V
V+ V-
10
PW 5 D 25% PER 20
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PW
TF
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E1 E GA IN = 4 MU R1 520
+ -
+ -
Sawtooth Gen.
V4
Control 0 Signal
For Closed-loop, the control signal is compared with a sawtooth waveform to produce the pulse waveform.
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PSpice Implementation
M2 IR F15 0 10 0uH V2 20 V 68 0uF 10
Gate Driver
E1 E GA IN = 1 MU R1 520
+ -
+ -
V5
Comparator E2
IN +OU T+ IN - OU TETABL E
TD = 0 TA BLE = (0 ,0 ( 200u ,12 ) TF = 1 0n V( %IN +, % IN-) PW = 10n 0PE R = 20u V1 = 1 V TR = { 20u- 20n} V2 = 4 V
Vpulse
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D = 50 %
Pulse
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D = 33%
Pulse
PER
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SI NE
V
V1 = -1 V1 V2 = +1 TD = 0 V2 TR = { (1/(F TRI *2))- 10n} VO FF = 0 TF = {( 1/(F TRI* 2)-1 0n)} VA MPL = { Ma} PW = 20n FR EQ = {F SIN E} PE R = {1/F TRI } PH ASE = { -90/ Mf }
0
PARAMETERS:
Ma = 0 .8 Mf = 2 1 FTRI = {FS INE *Mf } FS INE = 5 0 VD C = 100
Comparator
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0V
44ms
46ms
48ms
50ms
52ms
54ms
56ms
58ms
60ms
Time [ms]
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SI NE1
V
V1 = -1 V1 V2 = +1 TD = 0 TR = { (1/(F TRI *2))- 10n } TF = {( 1/(F TRI *2)-1 0n)} PW = 20n PE R = {1/F TRI }
0.5 *VD C*( V(SI NE1 )-V( TRI) )/AB S(V (SIN E1) -V(TRI)) A
V
0
SI NE2
V
Comparator 1
PARAMETERS:
Ma = 0 .8 V2 a Mf = 2 1 FTRI = {FS INE *Mf } VO FF = 0 VA MPL = { Ma} FS INE = 5 0 FR EQ = {F SIN E} VD C = 100 PH ASE = { -90/ Mf +180}
0.5 *VD C*( V(SI NE2 )-V( TRI) )/AB S(V (SIN E2) -V(TRI)) B
V
Comparator 2
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0V
-1.0V
V(SINE1) 100V V(SINE2) V(TRI)
0V
44ms
46ms
48ms
50ms
52ms
54ms
56ms
58ms
60ms
Time [ms]
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Analog Behavior Model (ABM) Makes the Circuit Simpler Use equations to model circuits
Comparator Single Phase Rectifier Three Phase Rectifier Buck Converter in CCM Single Phase Inverter
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V(-) V(+)
IF the voltage at the terminal V(+) is greater than the voltage at terminal V(-) the output V(out) is HIgh, otherwise the output is LOw.
V(-) V(+)
+
(3) Using I/O graph V(out)
V(+)-V(-) V(-)
0
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SI NE
V
V1 = -1 V1 V2 = +1 TD = 0 TR = { (1/(F TRI *2))- 10n } TF = {( 1/(F TRI *2)-1 0n)} PW = 20n PE R = {1/F TRI }
1
SI NE E1
ou t1
V
2
0
TR I
0
PARAMETERS:
Ma = 0 .8 Mf = 2 1 FTRI = {FS INE *Mf } FS INE = 5 0 VD C = 10
ou t2
V
TA BLE = (- 100 u,-10 ) (1 00u, 10) VD C*( V(SI NE) -V(TRI)) /ABS (V(S INE )-V( TRI ))
ou t3
V
NO 2 is implemented using ETABLE Others are implemented using ABM part NO 2 & NO 4 are suitable for Op-amp (Error Amplifier)
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0V
0V
48ms
50ms
52ms
54ms
56ms
58ms
60ms
Time [ms]
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D5 Db reak
D6 Db reak
0
in
V(out)=ABS(V(IN))
V1 VO FF = 0 VA MPL = 3 40 FR EQ = 50 E1 IN +OU T+ IN - OU TEV ALU E R1 b 1k
ABS(V(IN))
0 0
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+
V2
10 0uH
20 Vdc
V3
MU R1 520
Vd
0
68 0uF
RL
TD = 0 TF = 1 0n PW = 10u PE R = 20u V1 = 0 TR = 1 0n V2 = 1 2V
Vd = d*Vin
+
d Vin
E1 IN +OU T+ IN - OU TEV ALU E
10 0uH
Vd
-
68 0uF
RL
V(%IN+)*V( %IN-)
0
40
VDC
+ Vab b
Bipolar SPWM
E1 IN+ OUT+ IN- OUTEVALUE
SINE TRI
+ Vab 0
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#TIPS
There are many different ways to model the same thing. So, be creative! Use a simple model wherever possible to reduce modeling time and make simulation run faster and converge better!
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+ -
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SG3525
We do not need to have SG3525 model in PSpices library to simulate buck converter with VMC. To verify the controller design, all we need are functional models of these: Error Amplifier Comparator Sawtooth generator
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+ Error Amp.
+
Comparator
To MOSFET Driver
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Consider we know all circuit parameters. Our interest is to simulate the system.
Comparator
+ -
Error Amp.
+
Vref VP ULSE
Sawtooth
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Load Disturbance
How to set a load disturbance ? Let the load disturbance is:
3A
1A 0A
8 ms 8.5 ms
I1
ILOAD
Load Disturbance
How to set load disturbance ? Using SW_tclose and SW_topen
TOPE = 8.5m N 1 2
TCLOS = 8m E
2 .5
5//2.5 =1.666
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L1 out {L}
I V 0Vdc
ILOAD
I
IC = 1A
+ -
GA IN = 3
C1av {C} IC = 5V
{R2}
E2av OUT+ IN+ OUT- INE1av OUT+ IN+ OUT- INV1 V2 = 3 TD = 0 TR = {10u-20n} TF = 10n PW = 10n PE R = 10u ET ABLE -V(%IN+, %IN-)
{C2}
{R1}
{C1}
R4av
V2av R2 {Rbias}
{R3}
(0,0) (250u,5) V1 = 0 0
ET ABLE V(%IN+, %IN-)
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Output Voltage
5.0V
2.0A
Inductor Current
8.1ms
8.2ms
8.3ms
8.4ms
8.5ms
8.6ms
8.7ms 8.8ms
Time [ms]
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Input Disturbance
How to set an input disturbance ? Let the input disturbance is:
25 V
15 V
0V 8 ms 8.5 ms
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Input Disturbance
How to set an input disturbance ?
15 V
0V 8 ms 9 ms
PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)
Input Disturbance
Responses
30V 25V 20V 10V V(INPUT) 5.1V 5.0V 4.9V 4.8V V(OUT) 2.0A 1.0A 0A 7.8ms I(L1)
Input Voltage
8.0ms
8.2ms
8.4ms
8.6ms
8.8ms
9.0ms
9.2ms
9.4ms
9.6ms
9.8ms 10.0ms
Time [ms]
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Start-up Scenario
Previous simulation skips start-up scenario. To know how the controller handles start-up, set the initial values for iL and vc to zero.
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15
Inductor Current
10
Output Voltage
5
0 0s I(L1)
100us V(OUT)
200us
300us
400us
500us
600us
700us
800us
Time [s]
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Start-up Scenario
A very large overshoot and undershoot occur in inductor current.
The duty cycle is at first at 1 for a long time and later at 0 for a long time too, then after that it gradually increases. Convergence problem can easily occurs at this extreme condition.
5.0V
2.5V
Gate Signal
0V V(E1:1) 20 15 10 5 0 0s I(L1) 100us V(OUT) 200us 300us 400us 500us 600us 700us 800us
Time
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Start-up
In practical circuit, another auxiliary controller is required to handle start-up. This circuit is known as soft-start.
Soft start Controller
Gate Signal
0V V(E1:1) 20 15 10 5 0 0s I(L1) 100us V(OUT) 200us 300us 400us 500us 600us 700us 800us
5.0V
VMC Controller
2.5V
Time [s]
Soft-start circuit works by gradually increasing the duty cycle. So do the inductor current and capacitor voltage.
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Clock
+
+ Error Amp.
The output of SR flip-flop is set by the Clock. The output of SR flip-flop is reset by Comparator.
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Sawtooth
Error Amp. Comparator + + Analog Signals Digital Signals S SR Flip-flop
R
R R
Analog signals can be added at minus terminals of the comparator. Digital signals can be added at the input Resets of FF.
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Control Signal
Sawtooth is still compared with the control signal. But, Control Signal can be either Error Amp. output (EAO) or Soft-start signal (SS), whichever is lower.
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+
To R of SR Flip-Flop
Soft-start (SS)
C
The soft-start voltage is the capacitor voltage. The capacitor C is charged by a constant current source of 50 A. The result is a ramp voltage. C determines the duration of soft-start.
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V I C t
50 C
C = 125 nF
10 ms
+
To R of SR Flip-Flop
SS
C
EAO
Selector
Control Signal
We need a selector to select either SS or EAO, whichever is lower, to be Control Signal. We can use IF-Then-Else function IF(SS < EAO, SS, EAO)
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Soft-start In PSpice
SELECTOR IF-Then-Else
-V(%IN+, %IN-) C3av R6av{C3}
Error Amplifier
C2av R7av C4av
(0,0) (250u,5)
R E2av ET ABLE control OUT+ IN+ OUT- IN-
{R2}
E1av OUT+ IN+ OUT- INET ABLE -V(%IN+, %IN-)
{C2}
{R1}
{C1}
R4av
Vout
V2av R2 {Rbias}
{R3}
Comparator
0
V1 = 0 V2 = 3 TD = 0 TR = {10u-20n} TF = 10n PW = 10n PE R = 10u
TRAN = PWL(0,0)(10m,4)
Sawtooth Generator
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Soft-Start Signal
Control Signal
1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Time [ms]
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V(OUT)
tstart-up = 1ms
0V 4.0A
2.0A
I(L1)
0A 0s
1.0ms
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
C = 25 nF
V(OUT)
2.5V
tstart-up = 3.2 ms
0V 2.0A
1.0A
I(L1)
0A 0s
1.0ms
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
Time [ms]
Still has a small overshoot and undershoot in inductor current has a room for improvement by increasing C.
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V(OUT)
V(OUT)
0V 2.0A
1.0A
I(L1)
SEL>> 0A 0s 5ms 10ms 15ms Time 20ms 25ms 30ms 35ms
I(L1)
Sawtooth
Error Amp. Comparator + + Analog Signals Digital Signals S SR Flip-flop
R
R R
To add digital signals for protection. For examples, Maximum Duty Cycle and Current Limiter Flip-flop can be reset either by PWM comparator, or Maximum duty cycle, or Current Limiter.
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I(L1)
RESET 2 (CL)
1 2 1 U11A 7402 3 3
8A
SET S
V1 = 0 V2 = 5V TD = 0 TR = 1n TF = 1n PW = 0.1u PE R = 10u VClock
U16A 7432
ET ABLE
Set only by one i. e. the clock Reset can be done by three, whichever comes first.
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RESET 1 (EAO)
CLOCK
DUTYMAX
SAWTOOTH
DUTYMAX signal will only reset FF if the duty cycle is more than 0.85 This DUTYMAX is to make sure that the MOSFET always turns-off for each cycle CurrentLimit signal will only appear and reset FF if the peak switch is greater than pre-specified value.
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Output Voltage
5
Inductor Current
0 5.6ms V(OUT) 5.7ms I(L1) 5.8ms 5.9ms 6.0ms 6.1ms Time 6.2ms 6.3ms 6.4ms 6.5ms 6.6ms
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8A Limiter
Output Voltage
Inductor Current
0 5.6ms V(OUT)
5.7ms I(L1)
5.8ms
5.9ms
6.0ms
6.1ms
Time
6.2ms
6.3ms
6.4ms
6.5ms
6.6ms
Reset by EAO
Reset by DutyMax
Reset by CurrentLimit
Reset by EAO
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V(CLOCK)
5.0V 2.5V 0V
5.0V
2.5V 0V 5.0V 2.5V
V(PWMCOMP)
V(Q)
V(CURRENTLIM)
V(Q)
0V 5.90ms
V(DUTYMAX)
5.95ms V(Q)
6.00ms
6.05ms
6.10ms
6.15ms
6.20ms
Time [ms]
Knowing
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CONCLUSION
In order to simulate power electronic circuit:
Know how to program VPULSE for Pulse, Sawtooth, and Triangular waveforms. Avoid discontinuity at any cost Use the simplest model possible Use a simple model first, and add complexity in stages. No replacement for good understanding
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Q&A
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