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Table Of Contents

The Verilog Module
Outline of a Module
Example of a Module
Lab 1: Minilab Flip-Flop
Basic Verilog Data Types
Bits and Vectors: Bits
Bits and Vectors: Vectors
Bits and Vectors: Width Rules
reg Variables
reg Variable Example
wire Variables
wire Variable Connection
wire Variable Example
wire Variable Contention Example
integer Variables
integer Variable Example
End Verilog Variables
Basic Verilog Operators
Logical Operators
Bitwise Operators
Unary Bitwise Operators
Arithmetic Operators
Relational Operators
Shift Operators
Conditional Operator
End Basic Verilog Operators
Sequential RTL
RTL Procedural Control: if
RTL Procedural Control: case
RTL Procedural Control: for
RTL Expressions & Statements
Expressions & Statements in RTL Mux
Expressions & Statements in RTL Flip-Flop
RTL Last Statement Wins
RTL Blocking Assignment
Blocking Assignments in a Testbench
D Flip-Flop Testbench Example
D Flip-Flop Testbench, Clock Disentangled
RTL NonBlocking Assignment
NonBlocking Assignment in a Flip-Flop
NonBlocking Assignment in a Clock Generator
RTL Last Statement Wins, Again
End Basic RTL
Lab 2: Sequential Device
More on Verilog Operators
Operator List (complete)
Operator Precedence Table
The Concatenate Operator
End Verilog Operators
Sensitivity Lists
always Block Sensitivity
always Block Change Control
always Block Edge Control
initial Block Sensitivity
Continuous Assignment (assign) Sensitivity
Primitive Instantiation Sensitivity
End Simulation Control and Sensitivity
Latch Inference
Avoid Synthesis of Latches
A Good Transparent Latch Model
Latches and Muxes
Latching By Mistake
End Synthesis Issues
Lab 3: ALU Schematic
Lab 3: ALU Function Table
Day 2
Delays and Synchronization
Whence That Delay?
Blocking and Nonblocking Statements
Undelayed Blocking and Nonblocking Statements
Example of Undelayed Statements
Effect of Clocking by Nonblocking Assignment
Delayed Blocking and Nonblocking Statements
Clocks and Asynchronous Controls
Clock Inference
Asynchronous Control Priority
End Delays and Synchronization
Structural Design
Structural Design Port Mapping
Port Mapping by Name
Port Mapping by Position
Port mapping by position:
Verilog Primitive Gates
Verilog Logic Gate Examples
Verilog Buffer Gate Examples
Multivalue Delays
Simulation of wire Delays
Timing Triplets
Timing Triplet:
End Delays
Shift Registers
Verilog Shifting
Shift Register Schematic
Lab 4: Structural and RTL Shift Registers
Lab 4: Structural Shift Register
Lab 4: RTL Shift Register
Verilog Comments, Strings, and Messages
Verilog Comments
Compiler Directives (Macroes)
`define Compiler Directive Example
Timescale Compiler Directive
Verilog Simulator Strings
Verilog Messaging System Tasks
Verilog Message Format Specifiers
Numerical Format Width Specifiers
End Comments, Strings, and Messages
Vectors Again
Vector Selects
Vector Bit-Reversal
Arrays
Array Example: Simple RAM
End Vectors and Arrays
Modelling Sequential Logic
Review: Verilog Rules of Thumb
Lab 5 Introduction
Lab 5: Counter-Decoder Design
Lab 5: Decoder Basics
The Lab 5 Decoder
End of Verilog Course
Wrap-up Lecture: The Value of Synthesis
Wrap-up Lecture: Constructs Not Covered
Wrap-up Lecture: Parting Advice
That's It
P. 1
Verilog Two-Day Introductory Course Slides

Verilog Two-Day Introductory Course Slides

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This contains the instructor material for the authors two-day course on the Verilog language. The course presentation is posted elsewhere on Scribd.
This contains the instructor material for the authors two-day course on the Verilog language. The course presentation is posted elsewhere on Scribd.

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Categories:Types, Research
Published by: John Michael Williams on Feb 25, 2013
Copyright:Traditional Copyright: All rights reserved
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03/21/2013

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