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Table Of Contents

Digital Signal Processing Design Challenges
The Performance Gap
The Ideal Solution
XtremeDSP Slice Delivers Maximum Performance, Minimum Power, and Best Economy
Simplicity and Efficiency of the Cascade Logic
Extremely Low Power Consumption
Increased Flexibility for Cost Effectiveness
Easy to Use
Virtex-4 FPGAs ⎯A Platform for Every Application
Reduce Time-to-Market with World-Class Xilinx Support
A Must-Read
Introduction
Architecture Highlights
Number of DSP48 Slices Per Virtex-4 Device
DSP48 Slice Primitive
DSP48 Slice Attributes
Attributes in VHDL
Attributes in Verilog
DSP48 Tile and Interconnect
Simplified DSP48 Slice Operation
Timing Model
A, B, C, and P Port Logic
OPMODE, SUBTRACT, and CARRYINSEL Port Logic
Two’s Complement Multiplier
X, Y, and Z Multiplexer
Three-Input Adder/Subtracter
Carry Input Logic
Symmetric Rounding Supported by Carry Logic
Forming Larger Multipliers
FIR Filters
Basic FIR Filters
Creating FIR Filters
Adder Cascade vs. Adder Tree
DSP48 Slice Functional Use Models
Single Slice, Multi-Cycle, Functional Use Models
Single Slice, 35x18 Multiplier Use Model
Single Slice, 35x35 Multiplier Use Model
Fully Pipelined Functional Use Models
Fully Pipelined, 35x18 Multiplier Use Model
Fully Pipelined, 35x35 Multiplier Use Model
Fully Pipelined, Complex, 18x18 Multiplier Use Model
Fully Pipelined, Complex, 18x18 MAC Use Model
Fully Pipelined, Complex, 35x18 Multiplier Usage Model
Miscellaneous Functional Use Models
VHDL Instantiation Template
Verilog Instantiation Template
Overview
Dividing with Subtraction
Dividing with Multiplication
Square Root
Square Root of the Sum of Squares
Conclusion
Chapter 4
Single-Multiplier MAC FIR Filter
Bit Growth
Generic Saturation Level
Coefficient Specific Saturation Level
Control Logic
Embedding the Control Logic into the Block RAM
Rounding without an Extra Cycle
Using Distributed RAM for Data and Coefficient Buffers
Symmetric MAC FIR Filter
Dual-Multiplier MAC FIR Filter
Chapter 5
Parallel FIR Filters
Transposed FIR Filter
Advantages and Disadvantages
Resource Utilization
Systolic FIR Filter
Symmetric Systolic FIR Filter
Rounding
Performance
Semi-Parallel FIR Filter Structure
Four-Multiplier, Distributed-RAM-Based, Semi-Parallel FIR Filter
Data Memory Buffers
Coefficient Memory
Control Logic and Address Sequencing
Three-Multiplier, Block RAM-Based, Semi-Parallel FIR Filter
Other Semi-Parallel FIR Filter Structures
Semi-Parallel, Transposed, Four-Multiplier FIR Filter
Multi-Channel FIR Implementation Overview
Top Level
DSP48 Tile
Combining Separate Input Streams into an Interleaved Stream
Coefficient RAM
Implementation Results
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DSP: Designing for Optimal Results

DSP: Designing for Optimal Results

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Published by Roman Bacik
High-Performance DSP Using Virtex-4 FPGAs
High-Performance DSP Using Virtex-4 FPGAs

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Published by: Roman Bacik on Mar 02, 2013
Copyright:Attribution Non-commercial

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03/03/2013

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