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FUNCTIONAL TESTING OF A MICROPROCESSORTHROUGH LINEAR CHECKING METHOD
Prof. Dr. Pervez Akhtar
National University of Science & Technology,Karachi Campus, Pakistanpervez@pnec.edu.pk 
Prof. Dr. M.Altaf Mukati
Hamdard Institute of Information Technology,Hamdard University, Karachi, Pakistanaltafmukati@gmail.com
ABSTRACT
The gate-level testing also called low-level testing is generally appropriate at thedesign time and for small circuits. The chip-level testing and board-level testingalso called high-level testing are preferred when the circuit complexities are toohigh, making it difficult to perform low level testing in a reasonable amount of time. The cost of low-level testing is also generally very high. Such high costs andtime are only justified when some design-changes are required.
 
In this paper, ahigh level quick checking method, known as Linear Checking Method, ispresented which can be used to qualify the functionality of a Microprocessor. Thiscan also be used to check hard faults in Memory chips.
Keywords:
Microprocessors, ALU, Control Unit, Instructions.
1
 
INTRODUCTION
Due to the advances in the integrated circuittechnology, more and more components are beingfabricated into a tiny chip. Since the number of pinson each chip is limited by the physical size of thechip, the problem of testing becomes more difficultthan ever. This problem is aggravated by the factthat, in nearly all cases, integrated circuitmanufacturers do not release the detailed circuitdiagram of the chip to the users [1].The users are generally more interested to knowabout the chip, whether is it functionally workingand relied upon? if not, the whole chip is replacedwith a newer one. This is contrast to the gate-leveltesting of a digital circuit, which is used to diagnosefaulty gates in the given circuit, in case of failing.The idea of using functional testing is alsoaugmented by the fact that in case of any functionalfailure, caused due to any fault in the chip, the usercan not repair the chip. Hence the users have onlytwo choices: either to continue using the chip with aparticular failing function, knowing that the failingfunction will not be used in the given application orto replace the whole chip.The functional modeling is done at a higher levelof abstraction than a gate-level modeling. This in-fact exists between the Gate-level modeling and theBehavioral modeling, which is the highest level of abstraction [2]. The functional fault modeling shouldimitate the physical defects that cause change in thefunction or behavior, for example; the function of asynchronous binary up-counter is to advance onestage higher in binary value when clock hits it. Aphysical defect, which alters this function, can bemodeled in terms of its effect on the function. Suchdefect-findings are extremely important at the designtime or if the design changes are required at a laterstage.What, if a microprocessor does not produce thecorrect results of any single or more functions? Fromthe user’s perspective, it is enough to know whichfunction is failing, but from designer’s perspective,the cause of failing is also important to know, so thatthe design changes may be carried out, if necessary.This is certainly a time-taking process. For example,the gate level simulation of the Intel 8085microprocessor took 400 hours of CPU-time andonly provided 70% fault coverage [3].High level functional verification for the complexSystems-On-Chip (SOCs) and microprocessors hasbecome a key challenge. Functional verification andAutomatic Test Pattern Generator (ATPG) is onesynergetic area that has evolved significantly inrecent years due to the blossoming of a wide array of test and verification techniques. This area willcontinue to be a key focus of future MicroprocessorTEST and Verification (MTV) [4].
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Functional failures can be caused due to single ormultiple stuck-at faults in any of its functional block.The functional-testing, which refers to the selectionof tests that verify the functional operation of adevice, is one of an efficient method to deal with thefaults existing in a processor. Functional testing canalso be carried out at a smaller level, for example, afunctional test of a flip-flop might be to verifywhether can it be set or reset? and further, can it holdthe state or not? Similarly, the other MSI chips suchas Multiplexers, Encoders, Decoders, Counters,Hardwired-Multipliers, Binary-Adders & Subtrac-tors, Comparators, Parity Checkers, Registers andother similar circuits can also be verified for theirrequired functionalities.Some designers and manufacturers provide built-in self-test (BIST) these days that generate the test onthe chip and responses are checked within the chipitself. However, the widespread use of suchtestability techniques is hampered by a lack of toolsto support the designer and by the additional cost inchip area as well as the degradation in performance[5]. For example, the Intel 80386 microprocessoremploys about 1.8% area overhead for BIST to testportions of the circuit [6].The ever increasing complexity combined withthe advanced technology used in the design of themodern microprocessors, has lead to two majorproblems in producing cost-effective, high qualitychips:1
.
Verification: This is related to validate thecorrectness of the complex design. Simulationis the primary means of design validation usedtoday. In the case of processor designvalidation, the sequences are either writtenmanually or generated automatically by arandom sequence generator [7].
 
2. Testing: This is related to check themanufactured chips for realistic defects. Avariety of test generation and design-for-testability (DFT) techniques is used to ensurethat the manufactured chips are defect-free.Both design verification and testing depend,therefore, on test sequences used to expose either thedesign faults or manufacturing defects. It has alsobeen found that manufacturing test patterngeneration can be used for design verification [8] andthat design verification techniques can be used tofind better manufacturing tests [9]. However, to findthe effective test patterns for either of the saidpurposes is not simple, due to high complexities of microprocessors. Hence the only effective methodleft is to develop the functional tests. Considerablework has been done in the field of microprocessorfunctional testing. One of such work, known as‘Linear Checking Method’ is presented in this paper.Before performing functional testing, functionaldescription of the chip must be known. In case of microprocessor, this can be obtained through itsinstruction set. The two most important functionalblocks of any microprocessor are the CU (ControlUnit) and the ALU (Arithmetic Logic Unit). All theinstructions, at low-level, are composed of Op-Codesand operands. An op-code, also called the Macro-instruction, goes to the CU, which decodes eachmacro-instruction into a unique set of micro-instructions. The operands go to the ALU, whichprocesses it according the tasks defined within themicro-instructions. In between these functionalblocks, there exists several registers for thetemporary storage of op-codes, decoded-instructionsand operands.The fault may occur at various places in theprocessors, causing it to function incorrectly. Someof the common faults are: Register Decoding Fault,Micro-Operation Decoding Fault (caused may be dueto internal defect to the CU), Data Storage Fault(caused may be due to Stuck-at Fault or PatternSensitive Fault in the memory inside theMicroprocessor), Data Transfer Fault (caused may bedue to Stuck-at Fault or Bridging Fault on the bussesconnecting the various functional blocks of aMicroprocessor) or ALU Fault (caused due tointernal defect to the ALU). In each case, the givenmicroprocessor results in producing incorrectfunction/ functions.In the subsequent sections, first the functionalverification has been described in general and thenthe Linear Checking Method has been presentedthrough several examples. Based on the resultsobtained, the conclusion has been drawn and thefurther work has been proposed.
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FUNCTIONAL VERIFICATION
The micro-instructions from the CU and theoperands of an instruction are sent to the ALUsimultaneously. The ALU then carries out theintended task or function. This can be shown withthe help of a block diagram, as in Fig. 1.
Figure 1:
Functional testingThe typical instructions are ADD, SUB, MUL,
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SHL, SHR, ROTL, ROTR, INC, DEC, COMPL,AND, OR, XOR and many others.
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LINEAR CHECKING METHOD
This method can be used to test and verify, notonly the functionality of a microprocessor (morespecifically ALU), but the memories as well. Linearchecking is based on computing the value of ‘K’using the equation 3.1:
iiii
K = f(x, y) + f(x, y) + f(x, y) + f(x, y)
(1)
 
Equation 1 is called the ‘basic equation’. Thevariables x and y are the operands, ‘i’ is theinstruction. The value of K does not depend on thevalues of x and y, but only depends on the instructionand on the size of operands (number of bits in theoperands). It means the value of K is unique forevery instruction. The chances are very little that thetwo instructions may have the same constant value of K. An 8 and 16-bit ALUs have different values of K,for the same instruction. Hence, in this method, K isused as a reference value to verify the functionalityof an individual instruction.
3.1 Examples of functional verifications
Consider a 4-bit ALU. The value of ‘K’ can becomputed as follows:Suppose the instruction is ADD(x, y) = x + yHere, n = 4. Let x = 5 (0101) and y = 3 (0011)Therefore
x
= 1010 and
y
= 1100The value of K can be obtained from Equation 1,as follows:ADD(5,3)+ADD(5,12)+ADD(10,3)+ADD(10,12) = K8 + 17 + 13 + 22 = 60Hence, for a 4-bit ALU, the ADD instructionwill always be tested with respect to its referencevalue of 60, regardless what values of x and y aretaken, i.e. instead of 5 and 3 as in the above example,now these values are taken as 9 and 10 respectively.Still the value of K remains the same, as provedbelow:i.e. for x = 9 (1001) and y = 10 (1010)
x
= 6 (0110) and
y
= 5 (0101)ADD(9,10)+ADD(9,5)+ADD(10,6)+ADD(6,5)=60The generalized formula can also be developed tofind the value of K for the ADD instruction, for anysize of ALU, as follows:K
+
(n) = 4(2
n
– 1)Where, the subscript with K represents thefunction. Hence from the generalized form, weobtain the same value of K i.e. if n = 4, then K
+
(4) =4(15) = 60.Similarly, the value of K for any instruction canbe obtained, provided its functional description isknown. The value of K, for the various otherfrequently used instructions, can be obtainedsimilarly, as follows:Again assume a 4-bit ALU. Taking x = 10 and y= 12 then
x
= 5 and
y
= 3 in all the computations.3.1.1
Multiply instruction (f(x,y) = X * Y)
f 
i
(x,y) = MPY(x,y) = X * YHence, from equation 3.1, the value of K can beobtained as follows:MPY(12,10)+MPY(10,3)+MPY(5,12)+MPY(5,3)120 + 30 + 60 + 15 = 225Generalized form
K
*
= (2
n
– 1)
2
3.1.2
Transfer instruction (f(x) = x)
This is a single valued function, hence only onevariable is taken in computation of K, thus ‘y’ isignored in equation 1.Thusi
f(x) = x
 = x + x +
x
+
x
= 10 + 10 + 5 + 5 = 30Generalized form
K = 2(2
n
– 1)3.1.3
Shift-Right instruction (f(x) = SHR(x))
It is also a single valued function. With x = 1010:(a)i
f(x, y)
&
i
f(x,y)
reduce to
i
f(x)
and(b)
i
f(x, y)
&
i
f(x, y)
reduce to
i
f(x)
 Now
i
f(x)
represents the value of x, after SHRoperation i.e. 1010
0101 andi
f(x)
represents thevalue of 
x
after SHR operation i.e. 0101
0010.Hence, K = 0101 + 0101 + 0010 + 0010or K = 5 + 5 + 2 + 2 = 14Generalized form
K = 2(2
n-1
– 1)3.1.4
Shift-Left instruction (f(x) = SHL(x))
With the same explanation as in section 3.1.3,the equation 1 becomes:iiii
K = f(x) + f(x) + f(x) + f(x)
 
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