library ieee;

use ieee.std_logic_1164.all;
entity comp2b is
port(x,y:in bit_vector(1 downto 0);
G,E,L:out bit);
end comp2b;
architecture BF of comp2b is
begin
process(x,y)
begin
if((x(1)='0' and Y(1)='0') or (x(1)='1'and y(1)='1'))
then if(x(0)='1' and y(0)='0')then
G<='1';L<='0';E<='0';
elsif(x(0)='0' and y(0)='1')then
L<='1';G<='0';E<='0';
elsif ((x(0)='0' and y(0)='0') or (x(0)='1' and y(0)='1')) then
E<='1';G<='0';L<='0';
end if;
elsif(x(1)='1' and y(1)='0') then
G<='1'; L<='0';E<='0';
elsif(x(1)='0' and y(1)='1') then
G<='0'; L<='1';E<='0';
end if;
end process;
end BF;