Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more ➡
Download
Standard view
Full view
of .
Add note
Save to My Library
Sync to mobile
Look up keyword or section
Like this
0Activity
×

Table Of Contents

2.1.INVERTER/NOT Gate
2.2.AND Gate
2.3.NAND Gate
2.4.OR Gate
2.5.NOR Gate
3.1.HALF ADDER (Rangkaian setengah penjumlah)
3.2.FULL ADDER (Rangkaian penjumlah penuh)
3.3.HALF SUBTRACTOR (Rangkaian setengah pengurang)
3.4.FULL SUBTRACTOR (Rangkaian pengurang penuh)
3.5.DEKODER
3.6.ENKODER
3.7.MULTIPLEKSER
3.8.DEMULTIPLEKSER
4.1.Penyederhanaan menggunakan dalil aljabar Boolean
4.2.Penyederhanaan dengan menggunakan metode K-MAP
4.2.1.Kondisi acuh (Don’t care condition)
4.2.2.Cara penggambaran map:
5.1.Sistem bilangan Desimal
5.1.1.Konversi ke sistem bilangan Biner
5.1.2.Konversi ke sistem bilangan Heksadesimal
5.2.Sistem bilangan Biner
5.2.1.Konversi ke sistem bilangan Desimal
5.2.2.Konversi ke sistem bilangan Heksadesimal
5.3.Sistem bilangan Heksadesimal
5.3.1.Konversi ke sistem bilangan Desimal
5.3.2.Konversi ke sistem bilangan Biner
6.1.2.Saklar/Switch
6.1.3.LED (Light Emiting Diode)
6.1.5.IC (Integrated Circuit)
6.2.Cara menarik garis penghubung antar komponen
6.3.Logic Converter
7.1.1.Bahasan tentang file *.pld
7.1.2.Bahasan tentang file *.si
7.2.1.Pembuatan PCB Wizard
7.2.2.Penempatan Komponen
7.2.5.Mengubah ukuran Pad
0 of .
Results for:
No results containing your search query
P. 1
Modul Rld

Modul Rld

Ratings: (0)|Views: 438|Likes:
Published by Pur Wanto

More info:

Published by: Pur Wanto on Mar 10, 2013
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as PDF, TXT or read online from Scribd
See More
See less

03/10/2013

pdf

text

original

You're Reading a Free Preview
Pages 5 to 48 are not shown in this preview.

You're Reading a Free Preview

Download
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->