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© 2002 Xilinx, Inc. All Rights Reserved
Course Agenda
Advanced Xilinx FPGADesign with ISE
 
Agenda -3
© 2002 Xilinx, Inc. All Rights Reserved
Agenda
Section 1 : Optimize Your Design for Xilinx Architecture
 –
Core Generator System
Lab : Core Generator System Flow
Section 2 : Achieving Timing Closure
 –
Timing Closure with Timing Analyzer 
 –
Global Timing Constraints
Lab : Global Timing Constraints
 –
Advance Timing Constraints
Lab : Achieving Timing Closure with Advance Constraints
Section 3 : Improve Your Timing
 –
Floorplanner 
Lab: Floorplanner 
Section 4 : ReduceImplementaionTime
 –
Incremental Design Techniques
Lab : IDT Flow
 –
Modular Design Techniques
Lab : MDT Flow
 
Agenda -4
© 2002 Xilinx, Inc. All Rights Reserved
Agenda
Section 5 : Reduce Debug Time
 –
FPGA Editor: Viewing and Editing a Routed Design
Lab: FPGA Editor 
Section 6 : On-Chip Verification and Debugging
 –
ChipScope Pro
Demo
Section 7 : Course SummaryOptional Topics
 –
Power Estimation with Xpower 
 –
Advance Implementation Options
 –
Embedded Solutions with Power PC/MicroBlaze and Embedded Development Kit (EDK)
 –
Xtreme DSP Solutions with System Generator 
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