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CAO-II Module 2 Complete

CAO-II Module 2 Complete

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Published by Asim Arunava Sahoo
cao notes complete module 2
cao notes complete module 2

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Published by: Asim Arunava Sahoo on Mar 08, 2009
Copyright:Attribution Non-commercial

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05/10/2014

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Pipeline
A substantial improvement in performance can be achieved by overlapping the executionof basic steps called pipe lining.
 Example
:
Suppose that we want to perform the combined multiply and add operationswith a stream of numbers.A
i
* B
i
+ C
i
for 
i
= 1,2,3,……,7Each sub operation is to be implemented in a segment within a pipeline. The suboperations performed in each segment of the pipeline are as follows:
R1 A
i
, R2 B
i
InputA
i
& B
i
R3 R1* R2, R4 C
i
Multiply & Input C
i
R5 R3 + R4 Add C
i
to productClock Pulse Number 
Segment 1Segment 2Segment 3R1R2R3R4R51A1B1---------2A2B2A1 * B1C1---3A3B3A2 * B2C2A1 * B1 + C14A4B4A3 * B3C3A2 * B2 + C25A5B5A4 * B4C4A3 * B3 + C36A6B6A5 * B5C5A4 * B4 + C47A7B7A6 * B6C6A5 * B5 + C58------A7 * B7C7A6 * B6 + C69------------A7 * B7 + C7Content of register in pipeline
 
AiBiCiR1R2Multiplier R3R4Adder R5
 
Example
:1.Suppose to execute n task there are
-segment pipeline with a clock cycle time of t
 p
.2.The first task T1 requires a time equal to kt
 p
 
to complete its operation using k segments in the pipe.3.The remaining n - 1 tasks emerge from the pipe at the rate of one task per clock cycle and they will be completed after a time equal to (n - l) t
 p
4.Therefore, to complete n tasks using a k-segment pipeline requires k + (n - 1)clock cycles.
S
PEEDUP
The speedup of a pipelining processing over an equivalent non pipelining processing isdefined by the ratio.S =
 p p
nnt 
)1(
+
As the number of tasks increases, n becomes much larger than k - 1, and k + n - 1approaches the value of n. Under this condition, the speedup becomesS =
 pn
If we assume that the time it takes to process a task is the same in the pipeline and non pipeline circuits, we will have
t
n
= kt
 p
.
Including this assumption, the speedup reduces toS =
 p p
kt 
= k This shows that the theoretical maximum speedup that a pipeline can provide is k,where k is the number of segments in the pipeline.
For example:
There are 4 segments t
1
=60ns,t
2
=70ns,t
3
=100ns, t
4
=80ns and the interface registers have adelay of tr=10ns 
Using Pipeline :
The clock cycle is chosen to be t
 p
= t
3
+ t
= 100 + 10 = 110ns
Using Non-pipeline:
t
n
= t
1
+ t
2
+ t
3
+ t
4
+ t
=60 + 70 + 100 + 80 + 10 =320nsThe pipeline adder has a speedup of 320/110 = 2.9ns
 
For example:
If a pipeline executes many tasks, the overhead of start-up and drainage can beignored and the effective throughput of the pipeline taken to be 1 task per cycle. In termsof instruction execution, this corresponds to an effective CPI (cycles per instruction) of 1.
Linear Pipeline Processor
Linear pipelines are applied for instruction execution, arithmetic computation, andmemory-access operations.A linear pipeline processor is constructed with k processing stages. Externalinputs (operands) are fed into the pipeline at the first stage S
1
. The processed results are passed from stage Si to stage S
i+1
for all i = 1,2, ... ,k -1. The final result emerges from the pipeline at the last stage S
.Depending on the control of data flow along the pipeline, we model linear pipelines intwo categories:1.Asynchronous2.Synchronous.
Asynchronous Model:
1.Data flow between adjacent stages in an asynchronous pipeline is controlled by ahandshaking protocol.2.When stage Si is ready to transmit, it sends a ready signal to stage S
i+1
. After stageS
i+l
receives the incoming data, it returns an acknowledge signal to Si.

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