Ansoft Designer® Design Verification provides an easy process for verifying common design rules by providing support for creating, checking, and fixing design layouts within a single tool.Design Verification (DV) uses rule sets and runs to define a particular check of the layout. A ruleset contains scripts that define the checks to be done, and a run defines the objects to be checked. Acombination of a rule set and a run is used to perform the DV check (or DV “run”).Each DV check has its own results that may be graphically viewed in the
or exported graphically to GDSII or other formats. A text summary of the results of the check isavailable to be viewed in the
or exported to a file.Rule sets, runs, scripts, and generated results are all persistent, and are contained in the Designer project file. Results are stored as solution data in the results file associated with the project file.Rule sets, runs, and scripts may be part of technology files to jump start new projects with existingDV checks.
Design Verification employs layout-constraint rules which ensure that the IC/PCB will operate asdesigned, given the manufacturing process. Using DV, layers have restrictions on size, aspect ratio,and separation that result from different physical, chemical, and lithographic process limitations, aswell as the electrical properties of the device.DV rules to enforce these restrictions can be complex and involve layer and connectivityinteractions. Before sending the IC/PCB layout to be manufactured, you should first verify thelayout using the DV software:
For IC, the manufacturing foundry specifies the restrictions. IC foundries require checkingwith an authorized DV rule set to guarantee the manufacturing.
For PCB, companies that create the board design often have their own restrictions that alsoincorporate additional restrictions which come from the board manufacturer.