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Design Verification

Design Verification

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Published by: redoctober24 on Mar 08, 2009
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04/21/2011

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Design Verification-2
Design Verification
Ansoft Designer® Design Verification provides an easy process for verifying common design rules by providing support for creating, checking, and fixing design layouts within a single tool.Design Verification (DV) uses rule sets and runs to define a particular check of the layout. A ruleset contains scripts that define the checks to be done, and a run defines the objects to be checked. Acombination of a rule set and a run is used to perform the DV check (or DV “run”).Each DV check has its own results that may be graphically viewed in the
Layout
 
Editor
or exported graphically to GDSII or other formats. A text summary of the results of the check isavailable to be viewed in the
Layout
 
Editor
or exported to a file.Rule sets, runs, scripts, and generated results are all persistent, and are contained in the Designer  project file. Results are stored as solution data in the results file associated with the project file.Rule sets, runs, and scripts may be part of technology files to jump start new projects with existingDV checks.
Rule Checking
Design Verification employs layout-constraint rules which ensure that the IC/PCB will operate asdesigned, given the manufacturing process. Using DV, layers have restrictions on size, aspect ratio,and separation that result from different physical, chemical, and lithographic process limitations, aswell as the electrical properties of the device.DV rules to enforce these restrictions can be complex and involve layer and connectivityinteractions. Before sending the IC/PCB layout to be manufactured, you should first verify thelayout using the DV software:
For IC, the manufacturing foundry specifies the restrictions. IC foundries require checkingwith an authorized DV rule set to guarantee the manufacturing.
For PCB, companies that create the board design often have their own restrictions that alsoincorporate additional restrictions which come from the board manufacturer.
 
Design Verification SetupDesign Verification-3
Vendors of DV software work with foundries to provide authorized sets of design rules to meet the process requirements.
Partial Rule Checking
It is common for the design verification of a full layout to take hours to run. Since it is not practicalto do such a check often, DV tools also provide partial design testing. Using a combination of complete and partial testing speeds up development time. Another time saver is using DV tools thatcan run directly from the layout editor database to avoid data translation.DV is time-consuming and execution speed is a consideration. However, the top priority isaccuracy. Both the foundry/manufacturer and company designing the IC/PCB rely on the accuracyof the results. False errors are better than missed errors, but they slow down the design cycle.
Graphical Data
The execution of a DV rule produces graphical data (polygon or edge/vector) showing location andexplanatory error messages. The error messages may be output on the screen and/or included in thefile of a generated report. One or more reports are created during a design verification run. Thegraphical data can be stored with the layout data or separately. Both the textual and graphicalresults can be used to locate and fix errors, but it is faster and more convenient to work with thegraphical results accessed by a layout editor.
Hierarchical Checking
Hierarchical checking is used to speed up design verification.Layouts that use hierarchy to partition segments of the layout enable DV programs to check identical segments only once and use the results for each placement. Note that the advantage of hierarchy is greatly reduced if there is interaction with other objects at other levels of hierarchy.Some DV tools analyze the actual layout hierarchy/geometry and then synthesize a hierarchicalview that works best for design verification. Users can also modify portions of the layout hierarchyto “flatten” or ignore portions for checking. The verification view of the hierarchy does not changethe actual hierarchy used in the layout.
Design Verification Setup
Design Verification uses rule sets and runs to define a particular check of the layout. A layout mayhave multiple rule sets defined and a rule set may have multiple runs defined. Results are stored for each run and may be viewed or exported graphically. A text summary of the results of the run is
 
Design Verification SetupDesign Verification-4
available to be viewed or exported to a text file. Items related to design verification are stored in the
Project Tree
under the
Design Verification
item.To define a rule set, right-click 
Design Verification
in the
Project
 
Tree
and choose
Add Rule Set
.

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