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vhdl lab programs

vhdl lab programs

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Published by edrredy

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Categories:Types, School Work
Published by: edrredy on Mar 09, 2009
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09/11/2013

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EXPT NO: PAGE NO:
FULL ADDER AIM:Design and verify full adder by using dataflow style with select statement.PROGRAM:Library ieee;use ieee.std_logic_1164.all;entity fa_select isport(a:in bit_vector(2 downto 0); s:out bit_vector(1 downto 0));end fa_select ;architecture beh of fa_select isbeginwith a selects<=("00")when"000",("10")when"001",("10")when"010",("01")when"011",("10")when"100",("01")when"101",("01")when"110",("11")when"111";end beh;SIMULATION OUTPUT: RESULT: Full adder using dataflow style with select statement is simulated andVerified.
 NARASARAOPET ENGINEERING COLLEGE -NARASARAOPET
 
EXPT NO: PAGE NO:
FULL SUBTRACTOR AIM: Design and verify full subtractor by using dataflow style with select statement.PROGRAM:library ieee;use ieee.std_logic_1164.all;entity flsub_select isport(a:in bit_vector(2 downto 0);s:out bit_vector(1 downto 0));end flsub_select;architecture beh of flsub_select isbeginwith a selects<=("00") when "000",("11") when "001",("11") when "010",("01") when "011",("10") when "100",("00") when "101",("00") when "110",("11") when "111";end beh;SIMULATION OUTPUT: RESULT: Full subtractor using dataflow style with select statement is simulated andverified.
 NARASARAOPET ENGINEERING COLLEGE -NARASARAOPET
 
EXPT NO: PAGE NO:
FULL ADDER AIM: Design and verify full adder by using dataflow style with select statementPROGRAM: Library ieee;use ieee.std_logic_1164.all;entity fa_select1 isport(a,b,c:in bit; sum,carry:out bit);end fa_select1;architecture df of fa_select1 isbeginwith bit_vector'(a,b,c) select(sum,carry)<=bit_vector'("00") when "000" ,bit_vector'("10") when "001",bit_vector'("10") when "010",bit_vector'("10") when "100",bit_vector'("01") when "110",bit_vector'("01") when "011",bit_vector'("01" )when "101",bit_vector'("11") when "111";end df;SIMULATION OUTPUT: RESULT: Full adder is simulated and verified
 NARASARAOPET ENGINEERING COLLEGE -NARASARAOPET

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