NARAYANA ENGINEERING COLLEGE: NELLORE/GUDUR DEPARTMENT OF ECE ACADEMIC YEAR: 2012 2013 SUBECTIVE QUESTIONS Subject: Digital integrated

d circuits Class : III B.TECH. I SEM Faculty: K.MURALI / A. SURENDRA REDDY ---------------------------------------------------------------------------------------------------------------------------Weekly Test-1 UNIT-I 1. a) Draw the resistive model of CMOS inverter circuit and explain its behavior for low and high inputs. b) CMOS dynamic electrical behavior with help of circuit diagram and transfer characteristics. 2. a) Explain how to estimate sinking current for low output and sourcing current for high output of CMOS gate. Nov 2011 set-3 Nov 2011 set-2 b) Analyze the fall time of CMOS inverter output with RL=100, VL=2.5V, CL=10PF.Assume VL as stable state voltage. 3. Nov 2011 set-2 01/08/2012

a) Draw the circuit for CMOS three input NAND gate and its logic diagram function table and explain it. b) Design CMOS transistor circuit that has the functional behavior f(z)=(A+B)(B+D)(A+D)

Explain the following terms with reference to CMOS logic (i) Logic levels (iii)Power Supply Rails (ii) Noise Margin (iv) Propagation delay Nov 2011 set-1 b) What is the difference between transmission time and propagation delay. Nov 2011

a) what are the parameters that are necessary to define the electrical characteristics of CMOS circuits?

6.

a) Design CMOS transistor circuit that has the functional behavior f(z)=((A+B)(B+C)) Nov 2010 set-3 Nov 2010 b) Design CMOS transistor circuit that has the functional behavior f(z)=((A(B+C))

a) what is the difference between transmission time and propagation delay? b) Compare HC, HCT, VHC and VHCT CMOS logic families with the help of output specifications with VCC from 4.5V to 5.5V. May 2011 Nov 2010

a) Design a 4_input CMOS AND_OR invert gate. Draw logic diagram and function table. Nov 2011 set-3, Nov 2011 set-1

b) Draw the CMOS circuit diagram of tri-state buffer .Explain the circuit with the help of logic diagram and function table Nov 2011 set-4

UNIT-II 1 a) Draw the circuit diagram of two input 10K ECL OR gate and explain its operation. b) Design a TTL totem pole NAND gate and explain the operation with the help of function table.

a) Mention the DC noise margin levels of ECL 10K family.

Nov 2011 set-4

b)A single pull up resistor to +5V is used to provide a constant 1 logic source to 15 different 74LS00 inputs. What is the maximum value of the resistor? How much high state DC noise margin can be provided in this case. 3 Nov 2011 set-4

a) Design a TTL three-state NAND gate and explain the operation with the help of function table. b) list out different categories of characteristics in a TTL data sheet .Discuss electrical and switching characteristics of 74LS00.

a) Explain the following terms with reference to TTL gate. (i) Voltage levels for logic 1 & logic 0 (ii) DC Noise margin (iii)Low-state unit load (iv)High-state fan out b) List out TTL families and compare them with reference propagation delay ,power consumption,speed power product and low level input current. 5 a) Design a three input NAND gate using diode logic and a transistor inverter? Analyze the circuit with the help of transfer characteristics. Nov 2010 set-3 Nov 2011 set-1 b) Draw the circuit diagram of 2-input LS TTL NOR gate and explain the functional behavior. Nov 2011 set-1

a) Explain sinking current and sourcing current of TTL output? which of the parameters decide the fanout and how? b) Design a TTL open collector NAND gate and explain the operation with the help of function table.

a) Compare CMOS,TTL and ECL with reference to logic levels,DC noise margin , propagation delay and fan out. characteristics of 74LS00? Nov 2011 set-2 Nov 2010 set-4 Nov 2011 set-3 Nov 2011 set-2 b) List out different categories of characteristics in a TTL data sheet ?Discuss electrical and switching

a) What are the interfacing circuits are used for CMOS/TTL interfacing? b) Explain about low voltage CMOS logic and interfacing.

Weekly Test-2

22/08/2012

UNIT-III 1 a) Discuss the steps in VHDL design flow. b) Explain the difference in program structure of VHDL and any other procedural language. Give an example. Nov 2011 set-4 2 3 4 5 a) Write the syntax of entity declaration in VHDL. b) Write the syntax of architecture body in VHDL. a) Write the entity declaration for full adder b) Write the entity declaration for 3 to 8 decoder a) Explain the use of packages. b) Write the syntax and structure of a package in VHDL. a) Explain the various data types supported by VHDL .Give the necessary examples. Nov 2010 b) Explain different data objects in VHDL .give one example for each one. 6 7 8 a) Explain about functions in VHDL? b) Write the syntax and structure of a function in VHDL.. a) Explain the use of libraries in VHDL give an example. b) Write the syntax and structure of a library in VHDL. a) Explain about procedures in VHDL? b) Write the syntax and structure of a procedure in VHDL.

Weekly Test-3

03/10/2012

UNIT-IV 1 a) Design the logic circuit and write a data flow style VHDL program for the following function F(X)= :

A, B,C , D (3,5,6,7,13) + d(1,2,4,12,15)

:

b) Design the logic circuit and write a data flow style VHDL program for the following function F(X)=

A, B,C , D (1,7,9,13,15)
Nov 2011 set-4

a) Explain with an example the syntax and the function of the following VHDL statements i) loop statement Nov 2011 set-2 b) Write a VHDL entity and architecture for a 3-bit synchronous counter using flip-flops ii) Case statement

a) Write a behavioral style VHDL program for the following functions. F(S) = A B F(

cI
c
Nov 2010

) = AB+A I +B I

b) Explain behavioral design elements of VHDL. 4 a) Write a VHDL entity and Architecture for the following function? F(X) = (a+b)(c+d). Also draw the relevant logic diagram b) Discuss the case statement and its use in VHDL program 5 Nov 2011 set-3

a) Write a process based VHDL program for the prime number detector of 4_bit input and explain the flow using logic circuit. b) Explain data flow design elements of VHDL . Nov 2011

6 7

a) Explain structural design elements of VHDL . b) Discuss the process statement and its use in VHDL program. a) Design a logic circuit to detect prime number of a 5-bit input. b) Write the structural VHDL program for the design.

a) what is the importance of time dimension in VHDL and explain its function? Nov 2010 set-2 b) Design the logic circuit and write a data flow style VHDL program for the following function F(X)= :

A, B,C , D (1,5,6,7,9,13)+d(4,15)
Nov 2010 set-1 UNIT-V

a) Design a 32 to 1 multiplexer using four 74X151 multiplexers and 74X139 decoder. b) Realize the following expression using 74X151 IC. F(y) =AB+BC+AC. Nov 2011

a) Using two 74X138 decoders design a 4 to 16 decoder. b) Write a data flow VHDL program for the above design. May 2011

3 4 5

a) Design a 3_input 5 bit multiplexer. Write the truth table and draw the logic diagram. b) Provide the data flow VHDL program for the design. a) Design a priority encoder that can handle 32 requests. Use 74X148 and required discrete gates. b) Explain the operation for the above design and provide the truth table. a) Draw the logic diagram, logic symbol of 74X151 and provide the truth table. b) Write a VHDL program for the above design using case statement. Nov 2011 set-4

a) Give the logic symbol for 74X138 and draw its logic diagram .Explain its operation with its truth table. this IC? Nov 2010 set-2 b) Draw the logic diagram of 74x283 IC and explain the operation .write dataflow VHDL program for

a) Design a 5 to 32 decoder using 74X 138. b) Explain the operation for the above design Nov 2010 set-4

a) Draw the logic symbol of 74X181. b) Write a VHDL program for the above design. Nov 2011 set-1

Weekly Test-4

20/10/2012

UNIT-VI

1.

Explain the operation of barrel shifter and write a VHDL code for a) Left shift b) Right shift Nov 2010 set-2

2 3

a) Design a barrel shifter for 8-bit using three control inputs. b) Write a VHDL program for the above design using data flow style. a) Write VHDL program for 8-bit comparator circuit. b) Using this entity write VHDL program for 24 bit comparator. Show the additional logic used for this purpose use structural style of modeling. Nov 2010

4.

a)Write VHDL program for 1_bit comparator circuit with the input bits equal ,less than ,greater than from previous stage and the outputs equal ,less than ,greater than. b) Write VHDL program for 16 bit comparator using dataflow style. Nov 2011 set-1 Nov 2010 set-4

a) A single floating point encoder converts 16-bit fixed-point data using four high order bits beginning with MSB . Design the logic circuit. b) Write a VHDL program for the above design using data flow style. May 2011

a) Design a 24 bit comparator using 74X682 ICs and discuss the functionality of the circuit. b) Write a VHDL program for the above design using data flow style. Nov 2011 set-2 Nov 2011 set-4

a) Design a 10 to 4 encoder with 1 out of 10 and outputs in BCD. b) Write a VHDL program for the above design using data flow style. May 2011

a) Design a 16 - bit comparator using 74x85 ICs. Draw the relevant circuit diagram. Nov 2011 b) Write a behavioral VHDL program to compare 16 bit signed and unsigned integers?

UNIT-VII 1 a) Distinguish between the synchronous and asynchronous counters Nov 2011 set-4 b) Design a 4 bit ripple counter using four T flip flops and no other components. Nov 2011 set-1

a) Distinguish between latch and a flip flop. Show the logic diagram for both. Explain their operation with truth tables Nov 2010 set-1 Nov 2010 set-1 b) Write a VHDL program for D flip flop in behavioral mode. Nov 2011 set-2 Nov 2010 set-1

a) Design a conversion circuit to covert a T flip flop to JK flip flop. b) Write a VHDL program for JK flip flop in behavioral mode.