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Embedded Systems
Lab Experience Guide
Speeding up the execution of the Viterbi decoding algorithmby adding custom instructions to a Nios-based system
Matteo Bosio 148451Patrick Chiapello 152123
 
 Note
:
the experience you're about to start was prepared for a 3-hour lab; the durations you find at the beginning of each paragraph are the reasonable time that every step should take to finish theexperience in three hours. However, if you're able to quickly complete the first fully-guided paragraphs, you will have more time for the part in which you will actually have to implement your own work (paragraphs from
 
Profiling the code
on).
Introduction (5 mins)
The aim of this experience is to gain familiarity with the possibility of adding extra instructions to anFPGA-based microprocessor, in order to increase the performance of the CPU on a specific application(in this case the Viterbi decoding algorithm).The Viterbi decoding algorithm is a quite complex procedure, which may be hard to understand forpeople that is not involved in signal processing; however it is NOT needed to understand in depth thesteps of the algorithm! What you just have to do, is to identify the most time consuming part of theprocedure, and then create some instructions that will speed up its execution.If you're interested in the details of the Viterbi algorithm, you can refer to the web page:http://home.netcom.com/%7Echip.f/viterbi/tutorial.htmlThe code used as a basis for the experience is the one you can find in the above link, however it's beennecessary to modify it, since it was too memory-consuming to fit in our system.We had to neglect the convolutional encoding part and the Gaussian white noise addition (Niosbase-processor doesn't have a floating point unit!), and so we will just feed the decoding function bymeans of a sequence of -1 and +1.The code you will work on is: files\viterbi.c
Setting up the system (40 mins)
In order to execute the code, we need to create a system on the FPGA board with the followingcomponents:
Nios CPU: is the cpu that actually executes your program
On-chip memory: the memory on which our program and our variables are stored
JTAG Uart: allows you to communicate with the PC (vital for debugging!)
Interval timer: useful for code profiling.In order to begin the design we need to open the development environment Quartus II. From the filemenu select ‘‘New Project Wizard’’ and click Next. From Explorer, create a working directory (forexample c:\viterbi ). Pay attention: do not use datapaths that contain blank spaces!From Quartus Project Wizard select the created directory as working directory, chose “nios_system” asproject name and “nios_system” as top level entity name. Then press next and skip the second tabpressing next again.
 
As FPGA chose the Cyclone II EP2C35F672C6 and than press finish button. Now that you have set upa project we have to add the Nios sub-system. Click on Tools SOPC Builder and choose
→
 “nios_system” as System Name. Be careful to choose VHDL as implementation language. On the leftside of the tool you have all the components you can add to the system. The first operation is adding aNios II processor. Look for the component in the left-side list and add it to the design by double-clicking it. In the following wizard select NIOS II/e (RISC, 32-bit) then press finish.Following the same procedure, add to your system the “jtag uart” component (“Communication”menu),45kB of on-chip memory (“Memory” menu) and two Interval timers (“Other” menu). Now your systemis almost ready. In the system menu press “auto-assign-base-addresses” and you are ready to generateyour code. Press Generate to create your Nios II system. Before implementing the design we need toassign pin location at list for two important signals: clock and reset. To do so, we first need the systemto complete Synthesis and Implementation process, so press the Start Compilation Button in theQuartus environment, but you can stop the process as soon as the Synthesis and Implementation phaseis completed. Now, from Quartus open Assignments Pin Planner and select the location PIN N2 for
→
 the clock and reserve it as a tri-state input. The reset signal is the Key[0] push button in location PING26 and it is an input as well. We are ready for the implementation. Close the Pin Planner and press onthe Start Compilation Button. If everything is alright you should obtain a successful compilation andyour design is ready to be tested. But our system is composed of a processor, so to test it we need toinstruct the processor to do something.In the next section how to complete this task will be explained.
Running the software (20 mins)
Now that we have a complete (and hopefully functional) hardware, we are interested in writing somesoftware to use it. From the Sopc-builder interface it is possible to execute the Software IDE (menutools). From Explorer you created a new folder (for example c : /viterbi/ ), now choose it when the toolprompt asks you for the project folder location. Now from menu file you chose new-project and selectAltera Nios II C/C++ application, click Next. Give a name to your software and selectHello_world_small in Select Project Template, then click Finish. Now select all the lines in the .C fileand replace them with the code you have in the file: files\viterbi.c. From the menu Project select Buildall to create the executable for your processor.Up to now we have built a system from scratch and compiled some software for it. Now, our task is tofind out whether what we have done is working or not. The first step is connecting the DE2 board(Blaster port) to the usb of your lab PC. Then you have to connect the power supplier and press the redbutton on the board. If you see a lot of led flashing and the message Welcome to the Altera DE2 boardon the display, you are ready to test your design. Next step is programming the FPGA with your design.From Quartus open Tools Programmer, then press Hardware setup and look for the usb-blaster
→
 interface. Then you mark the Program/configure flag and press start. On success a window labeledOpenCore Plus Status will appear telling you your system is running.
Do not close
the window or yoursystem will stop working. From the Nios IDE now you can try to execute your software. Open the runmenu, select run as and select Nios Hardware. The program calls 1000 times the function sdvd() andeach time the function is called, it prints an increasing number (from 0 to 999). In the end you'll see asequence of zeros and ones, which are the decoded sequence. You should compare it with the bitsequence contained in the files\bit_sequence.txt and check that they are identical.
 Note
:
if you press the Key[0] button, your program will restart from the beginning, since you assigned the reset to the pin associated to this button.
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