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Fault Tolerant Processor Using Hybrid Hardware Redundancy

Fault Tolerant Processor Using Hybrid Hardware Redundancy

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Our report regarding the design of a fault tolerant processor, using the Nios II cpu on a DE2 board. By Matteo Ainardi, Vittorio Giovara, Alberto Grand and Fabio Margaglia
Our report regarding the design of a fault tolerant processor, using the Nios II cpu on a DE2 board. By Matteo Ainardi, Vittorio Giovara, Alberto Grand and Fabio Margaglia

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Categories:Types, School Work
Published by: Project Symphony Collection on Mar 17, 2009
Copyright:Attribution Non-commercial

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07/07/2010

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Programmable System Design Testing and Design for Reliability of Digital Systems
Interdisciplinary Project
Fault Tolerant Processor
using Hybrid Hardware Redundancy 
Matteo AinardiVittorio GiovaraAlberto GrandFabio MargagliaMarch 11, 2009
 
Contents
2.1 Finite State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2
module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.2 Memory Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1
 
List of Figures
2.1 System Architecture Model. . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2 Main Finite State Machine Scheme. . . . . . . . . . . . . . . . . . . . . . . 92.3 Finite State Machine Scheme for the process
. . . . . . . . . . 112

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