Welcome to Scribd, the world's digital library. Read, publish, and share books and documents. See more
Download
Standard view
Full view
of .
Look up keyword
Like this
2Activity
0 of .
Results for:
No results containing your search query
P. 1
Stld Question Bank

Stld Question Bank

Ratings: (0)|Views: 944|Likes:
Published by rachasaikiran
STLD QUESTION BANK
STLD QUESTION BANK

More info:

Published by: rachasaikiran on Apr 02, 2013
Copyright:Attribution Non-commercial

Availability:

Read on Scribd mobile: iPhone, iPad and Android.
download as DOCX, PDF, TXT or read online from Scribd
See more
See less

08/25/2014

pdf

text

original

 
 Sreyas Institute of Engineering & Technology
Nagole, Hyderabad - 500 068.
Department of ECE
 Course :II-B.Tech Subject:STLDImportant Questions Unitwise
QUESTION BANK
Unit-1
1.
 
(a) Convert the following numbers:i. (6753)8 to base 10 ii. (00111101.0101)2 to base 8 and base 4 iii. (95.75)10 to base 2.(b) Represent +65 and -65 in sign-magnitude, sign-
1’s complement and sign
-
2’s
 Complement representation.2.
 
Given a = 10101001 and b = 1101 find:i. a + b ii. a
 –
b iii. a . b iv. a / b.3.
 
What is the Gray code? What are the rules to construct Gray code? Developthe 4 bit Gray code for the decimal 0 to 15.4.
 
What are the rules for XS3 addition? Add the two decimal numbers 123 and658
 
XS3 code.5.
 
Define a single error correcting code for a 11 bit group 01101110101
Unit-2
1.
 
State and prove the following Boolean laws:i. Commutative ii. Associative iii. Distributive.2.
 
Simplify the following Boolean functions to minimum number of literals:
i. ( a + b )’ ( a’
 
+ b’ )ii. y(wz’ + wz) + xy
 3. State Duality theorem. List Boolean laws and their Duals.4. Prove that OR-AND network is equivalent to NOR-NOR network and AND-OR network isequivalent to NAND-NAND network.
 
5.
For the given Boolean function F=xy’z+x’y’z+w’xy+wx’y+wxy
i. Draw the logic diagram ii. Simplify the function to minimal literals using Boolean algebra.
Unit-3
1.
 
Simplify the following Boolean expressions using K-map and implement them using NOR gates:
F (A, B, C, D) = AB’C’ + AC + A’CD’
 2.
 
List the Boolean function simplification rules using Tabulation method.3.
 
Simplify the Boolean function using K-map and implement using NAND gates
F=Σm(0,2,3,4,5,6)
 4.
 
Reduce the given function using tabular minimization method
F(A,B,C,D)=П(0,1,3,4,
5,6,7,8,9)+d(10,11,12,13,14,15)5.
 
Simplify the Boolean expression using K-map F=A
1
+AB+ABD
1
+AB
1
D
1
+C
Unit-4
1.
 
Implement the following Boolean functions using decoder and OR gates:F1(A,B,C,D) =
(2,4,7,9), F2(A,B,C,D) =
(10,13,14,15)2.
 
What is Hazard in switching circuits? Explain the design of Hazard freeSwitching circuit with an example.3.
 
What is Encoder? Design Octal to Binary Encoder.
4.
 
Design a combinational circuit that converts a decimal digit from 8, 4,-2,-1 code to 8,4,2,1 BCDcode.
 
5.
 
Design a combinational circuit that accepts a 3 bit number and generates an output binarynumber equal to the square of the input number.
Unit-5
1.
 
Implement the following boolean functions using PLA.f1(w,x,y,z) = P(0,1,3,5,9,13) , f2 (w,x,y,z) = P(0,2,4,5,7,9,11,15).2.
 
The following memory units are specified by the no of words times the number of bits per word.How many address lines and input-output data lines are needed in each case?i. 4K × 16 ii. 2G × 8 iii. 16M × 32 iv. 256K × 64. Give the number of bytes stored in thememories listed above.
 
3.
 
(a) Draw the basic macro cell logic diagram and explain.(b) Explain the general CPLD configuration with suitable block diagram.4.
 
For a given 3-input, 4-output truth table of a combinations ckt, tabulate the PAL programmingtable for the ckt.Inputs Outputx y z A B C D0 0 0 0 1 0 00 0 1 1 1 1 10 1 0 1 0 1 10 1 1 0 1 0 110 0 1 0 1 010 1 0 0 0 111 0 1 1 1 011 1 0 1 1 1
 
5. Write a brief notes on
a) Architecture of PLD’s. b)Capabilities and limitations of threshold gates.
 
UNIT-6
1.
 
Design Mod-6 synchronous coun
ter using JKFF’s.
 2.
 
Explain the followinga.
 
Race around condition in FF’s.b) JK master slave FF. c)Excitation table for FF’s.
 3.
 
Draw the logic diagram of a SR latch using NOR gates. Explain its operation using excitation table.4.
 
(a) Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.(b) Draw the block diagram of a 4 - bit serial adder and explain its operation.5.
 
a) Show that the characteristic equation for the complement out put of a JK flipflop is
 
(t + 1) = J ‘Q 
+ kQ.b)Discuss about mod-
6 synchronous counter using JK FF’S.
 
Unit-7
1.
 
Find the state table for the following state diagram

Activity (2)

You've already reviewed this. Edit your review.
1 thousand reads
1 hundred reads

You're Reading a Free Preview

Download
scribd
/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->