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HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS

HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS

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In regular FIR structure, by pipelining the multipliers one
can improve the throughput. But as the growth of operand
word length, the delay in addition process becomes another
important constraint. In this paper, a novel fine-grain
pipelining scheme for high throughput FIR is proposed. By
pipelining multipliers and adders, very high throughput can
be achieved. 2-Dimensional pipeline gating technique is used
to make the designed FIR power aware to the precision of the
operands. The average power dissipation and latency are
both significantly reduced with changing of input precisions.
In regular FIR structure, by pipelining the multipliers one
can improve the throughput. But as the growth of operand
word length, the delay in addition process becomes another
important constraint. In this paper, a novel fine-grain
pipelining scheme for high throughput FIR is proposed. By
pipelining multipliers and adders, very high throughput can
be achieved. 2-Dimensional pipeline gating technique is used
to make the designed FIR power aware to the precision of the
operands. The average power dissipation and latency are
both significantly reduced with changing of input precisions.

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Published by: Md Ibrahim Khalil Salman on Apr 18, 2013
Copyright:Attribution Non-commercial

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04/18/2013

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