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CAO-2 Model Test Paper 1

CAO-2 Model Test Paper 1

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Published by Asim Arunava Sahoo
model test
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Published by: Asim Arunava Sahoo on Mar 27, 2009
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Computer Architecture & Organization - II
Model Set - I
1. (a)
 
Why does pipelining improve performance?(Year-2008)Solution:
1.Pipeline is an implementation technique in which multiple instructions are overlapped inexecution. Today’s processors are fast because of pipelining.2.A pipeline is like an assembly line: each step completes one piece of the whole job. Assembleline does not reduce the time it takes to complete an individual job; it increases the amount of job being built simultaneously and the rate.3.Pipe stage (pipe segment) small piece of the pipeline instruction.4.Therefore, pipelining improves instruction throughput rather than individual instructionexecution time. The throughput of the instruction pipeline is determined by how often aninstruction exists in pipeline.5.The goal of designers is to balance the length of each stage; otherwise there will be idle timeduring a stage. If the stage are perfectly balanced then the time between instructions on the pipelined machine is = Time between instructions (no pipelined)/Number of pipe stages.
 (b) Differentiate between RISC and CISC @ machines. (Year – 2008)Solution:RISC (Reduced Instruction Set Computer).
A computer with fewer instructs with simple constructs, so they can be executed much faster withinthe CPU without having to use memory as often. This type of computer is classified as a reducedinstruction set computer or RISC.
RISC characteristics
(i)Relatively few instructions.(ii)Relatively few addressing modes.(iii)Memory access limited to load and store instructions.(iv)All operations done within the registers of the CPU.(v)Fixed length, easily decoded instruction format.(vi)Single cycle instruction execution.(vii)Hardware rather than micro programmed control.
CISC. (Complexes Instruction set Computer)
A computer with large number of instructions is classified as a complex instruction set computer.Characteristics of CISC.(i)A large number of instructions typically from 100 to 250 instructions.(ii)Some instructions that perform specialized tasks and are used infrequently.(iii)A large variety of addressing mode typically from 5 to 20 different modes.(iv)Variable length instruction format.(v)Instructions that manipulate operands in memory.
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(c) Why the performance of a parallel computer is improved by using a two level cachememory? (Year - 2008)Solution:
Modern high end PCs and workstations all have at least two levels of caches: A very fast, and hence notvery big, first level (L1) cache together with a larger but slower L2 cache. Some recent microprocessorshave 3 levels.When a miss occurs in L1, L2 is examined, and only if a miss occurs there is main memory referenced.So the average miss penalty for an L1 miss is
(L2 hit rate)*(L2 time) + (L2 miss rate)*(L2 time + memory time)
We are assuming L2 time is the same for an L2 hit or L2 miss. We are also assuming that the accessdoesn't begin to go to memory until the L2 miss has occurred.
(d)
Write at least four differences between a multiprocessor and multicomputer system. (Year - 2008)
Solution:Multiprocessor: -
 1.
Multiprocessor is more than one CPU or one CPU with more than one core in one.Multiprocessing is the use of two or more central processing units (CPUs) within a singlecomputer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them.2.A multiprocessor system is simply a computer that has more than one CPU on its motherboard. If theoperating system is built to take advantage of this, it can run different processes (or different threads belonging to the same process) on different CPUs.3.There are many variations on this basic theme, and the definition of multiprocessing can vary withcontext, mostly as a function of how CPUs are defined (multiple cores on one die, multiple chips in one package, multiple packages in one system unit, etc.).4.Multiprocessing sometimes refers to the execution of multiple concurrent software processes in a systemas opposed to a single process at any one instant. However, the terms multitasking or multiprogrammingare more appropriate to describe this concept, which is implemented mostly in software, whereasmultiprocessing is more appropriate to describe the use of multiple hardware CPUs.
Multicomputer: -
1.
Computer multicomputer is more than one computer or a network of computers. A computer made up of several computers. Something similar to parallel computing.2.A multicomputer may be considered to be either a loosely coupled NUMA computer or a tightly coupledcluster. Multicomputers are commonly used when strong computer power is required in an environmentwith restricted physical space or electrical power.3.Distributed computing deals with hardware and software systems containing more than one processingelement or storage element, concurrent processes, or multiple programs, running under a loosely or tightlycontrolled regime.4.In distributed computing a program is split up into parts that run simultaneously on multiple computerscommunicating over a network. Distributed computing is a form of parallel computing, but parallelcomputing is most commonly used to describe program parts running
simultaneously on multiple
 processors in the same computer.
(e)Discuss anti-dependence / Name-dependence Vs True dependence. (Year - 2006)Solution:
Anti-dependency
occurs when an instruction requires a value that is later updated. In the followingexample, instruction 3 anti-depends on instruction 2 - the ordering of these instructions cannot be
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changed, nor can they be executed in parallel (possibly changing the instruction ordering), as this wouldaffect the final value of A.1. B = 32. A = B + 13. B = 7
Anti-dependency is an example of a name dependency. That is, renaming of variables couldremove the dependency, as in the next example:
1.B = 3 N.B2 = B2.A = B2 + 13.B = 7A new variable, B2, has been declared as a copy of B in a new instruction, instruction N. The anti-dependency between 2 and 3 has been removed, meaning that these instructions may now be executed in parallel.
True dependence.
However, the modification has introduced a new dependency: instruction 2 is now truly dependent oninstruction N, which is truly dependent upon instruction 1. As true dependencies, these new dependenciesare impossible to safely remove.
(f)
What do you mean by cache coherence? (Year - 2006)Solution:
In a shared memory multiprocessor with a separatecache memoryfor each processor , it is  possible to have many copies of any one instructionoperand: one copy in the main memory andone in each cache memory. When one copy of an operand is changed, the other copies of theoperand must be changed also. Cache coherence is the discipline that ensures that changes in thevalues of shared operands are propagated throughout the system in a timely fashion.There are three distinct levels of cache coherence:1.Every write operation appears to occur instantaneously.
2.All processes see exactly the same sequence of changes of values for each separate operand.
3.Different processes may see an operand assume different sequences of values. (This isconsidered noncoherent behavior.)In both level 2 behavior and level 3 behavior, a program can observestale data. Recently,computer designers have come to realize that the programming discipline required to deal withlevel 2 behavior is sufficient to deal also with level 3 behavior. Therefore, at some point onlylevel 1 and level 3 behavior will be seen in machines.
(g) Explain what structural hazard with suitable example.Solution:
It occurs when combinations of instructions cannot be accommodated because of resource conflicts.Often arise when some functional unit is not fully pipelined. Load uses register file’s Write portduring its 5 th stage.12345Load IF RF/ID EX MEM WBR-type uses register file’s write port during the 4
th
stage.
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