Welcome

What Design Engineers Need To Know

Elements of FPGA:

 Basic FPGA Structures System Design Considerations Tools and Design Flow Lattice FPGAs

FPGA Field Programmable Gate Array

Customizable IC that is ASIC alternative High capacity and performance suitable for SOC No Mask Cost Configurable after manufacture Quick design implementation and revision From-stock delivery Shared volume pricing

Major Elements of an FPGA

Array of Logic Blocks (not simply gates) Programmable Interconnect I/O System elements Serial I/O Memory Processor/CPU MAC/DSP

FPGA Logic Cells

Many different names (LE, LC) LUT (look up table) 3-6 inputs MUX (multiplexer) Extends LUT input range Register/Latch/Storage Synchronous design Other elements vary with vendor Fast carry logic Full adder Counter Shift Register

LUT Provides Combinatorial Logic

ab c d y
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1

Replaces what once really were gates 3-6 inputs Output determined by truth table

LUT Implies Memory

4-input LUT gives 16-bit storage Combine LEs for various configurations NxM single port RAM Nx(M/2) dual port RAM NMx1 single port RAM ROM Etc.

Programmable Logic Hierarchy

Necessary to reduce interconnect overhead (more later) Terminology varies with vendor and generation Logic Cell One LUT and latch Slice Two or more tightlyinterconnected logic cells May include additional MUX Logic Block Locally interconnected slices Largest tightly-connected unit

Programmable Logic Hierarchy

Necessary to reduce interconnect overhead (more later) Terminology varies with vendor and generation Logic Cell One LUT and latch Slice Two or more tightlyinterconnected logic cells May include additional MUX Logic Block Locally interconnected slices Largest tightly-connected unit

Programmable Logic Hierarchy

Necessary to reduce interconnect overhead (more later) Terminology varies with vendor and generation Logic Cell One LUT and latch Slice Two or more tightlyinterconnected logic cells May include additional MUX Logic Block Locally interconnected slices Largest tightly-connected unit

Embedded Memory Blocks

Dedicated memory structures (versus LUT) For larger/faster memory needs Configurable Width/depth Type (single/dual port) Amount varies with vendor and device

Input/Output
General purpose I/O Configurable single-ended/differential Configurable logic level Configurable input termination Configurable edge rate SERDES For high-speed serial protocols Includes PHY Includes PCS Physical coding sub-layer, i.e., 8b/10b, etc. Analog Specialty devices that also include ADC/DAC, etc.

Multiply and Accumulate (MAC)

Supports DSP functionality Depth, resolution vary by vendor

Processor Core

For complex, relatively slow operations Often industry-standard architecture like ARM Varies by vendor

Programmable Interconnect

Programmable Interconnect

S=

Interconnection Hierarchy

Local to global Within a slice to across the chip Balances loading, trace length/delay, connectivity Part of vendor secret sauce

System Design Considerations

Power/speed/cost/density Overhead in FPGA compared to ASIC in same process Generally only a generation behind Device power Typically different voltage needs for core, I/O FPGA Configuration RAM-based Flash-based Antifuse FPGA Architecture

RAM-based FPGA
SRAM stores configuration Quick programming and reprogramming in circuit Volatile (needs power to maintain configuration) Typically needs supporting device for configuration storage Configuration data accessible

Flash-based FPGA
EEPROM stores configuration Non-volatile Can be programmed offboard Slower programming and reprogramming in circuit Needs additional programming voltage Configuration data more secure Requires effort to extract

Antifuse-based FPGA
Antifuse is insulator you burn out to make conductive Non-volatile One-time programmable only, off board Configuration data secure Needs electron microscope to probe

Other FPGA Architectural Features to Consider

Granularity Block size and embedded IP affect complexity, speed, utilization tradeoffs Embedded Memory Block size and placement, memory structure (multiport) affect speed Power Control Reduce average power by shutting down circuits not in use Clock Distribution/Domains Affects design flexibility, skew, power (via clock gating)

Designing with FPGAs

Forget about the underlying logic details (mostly) Tools handle the fine details Be prepared to override/force choices tools make Design at high level Verilog, VHDL MathLab Schematic capture (mostly block level) Use IP libraries Pre-designed common functions Vendor and 3rd party supplied Your companys unique IP Soft vs Firm IP Soft is circuit description only Firm includes implementation constraints

Design Tools and Flow

Many 3rd-party tools available Vendor-specific tools May need to Over-ride P&R Burn and Turn

Design Capture

Place and Route

Timing and Functional Simulation

Program and Test in-circuit

SRAM AND Flash-Based Programmable Solutions

Mid-Range

Low Density

Mixed Signal

Intellectual Property (IP)

Design Software

Development Boards

LatticeECP3: SRAM Based FPGA

3rd Generation Value-based FPGA 65nm SRAM Process 1.2v Core Voltage 17K to 150K LUTs Up to 7Mb Embedded RAM 16 Channels SERDES, ~110mW/Channel
250Mbps to 3.2Gbps Data Rates Supports PCIe, CPRI, GbE, XAUI, SMPTE

Lowest power SERDES- enabled FPGA

High Performance I/Os

1Gbps LVDS, DDR1/2/3

Full DSP Blocks up to 320 18x18 Multipliers

Bank 0 Bank Bank 7 Bank Bank 1 Bank
Bank Bank 8

Bank Bank 2 Bank Bank 3

Bank 6 Bank

SERDES SERDES

330MHz Fabric

3.2Gbps SERDES

>400MHz DSP Blocks

1Gbps I/Os

MACHXO2: Low-Cost, Low-Power Flash-based FPGA

Low cost
65-nm embedded Flash process Cost optimized architecture

Low power
As low as 19uW

High system integration

256 to 7K LUT logic density Up to 240K bits embedded memory User Flash memory Hardened I2C, SPI, timer/counter
Saves up to 600LUTs

THE DO-IT-ALL PLD

LATTICE DIAMOND FPGA DESIGN TOOL Built on existing foundation for cost sensitive, low power applications Key new features
Design exploration, Ease of use, Design flow improvement

Enhancements across all integrated tool views

Summary
You are now ready to explore your own FPGA design We covered
FPGA Silicon Features Software Capabilities Associated Embedded and Soft IPs

For more details on Lattice products:

www.latticesemi.com

Co-sponsors site with ECP3/XO2 promotional offers:

www.em.avnet.com/latecp3offer www.em.avnet.com/latmachxo2