Code: RA 9A04605

RA

B. Tech III Year II Semester (R09) Regular & Supplementary Examinations, April/May 2013 VLSI DESIGN (Electrical & Electronics Engineering) Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) (a) (b) Write short notes on etching process with neat diagram. Explain about different oxidation process. Derive Ids in different regions of MOS transistor. Consider nMOS transistor in a 180 nm process with W/L = 4/2 . In this process, the gate oxide thickness is 40 Ao and the mobility of electrons is 180 cm2 / V.s at 700C. The threshold voltage is 0.4 V. Plot Ids vs Vds for Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5, 1.8 V. Mention the three commonly used scaling models in VLSI. And clearly explain about them. (a) (b) (a) (b) 6 (a) (b) Realize the logic gates inverter, NAND and NOR gates using CMOS devices. Realize the logic operation [(A + B)*(C + D)]/ using CMOS. Write about switch logic and hence compare the properties of pass transistor and transmission gate used as switches in NMOS and CMOS respectively. Implement 8:1 multiplexers using CMOS switch logic. What are CLBs? With the help of internal architecture of CLBs explain how they are used in implementing the logical functions. With a diagram illustrating the internal architecture of PAL. Explain how logical functions are implemented using it. Explain how layout is optimized through placement and routing. (a) (b) Write about the testing of sequential circuits. Explain Iterative test generation method for testing sequential logic; mention the drawback of this method.

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