Direct Memory Access (DMA)
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What is DMA? A facility
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transfer data from memory to memory
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/ memory to peripheral
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memory and peripherals can be internal / external
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no intervention of CPU
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DMA controller takes care of memory transfer
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DMA has 6 channels for memory transfer
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Each channel connects to a source location and destination location
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Total 6 source and destination locations can be connected
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Single transfer at a time
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High priority channel is serviced before a low priority channel
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For same priority it is serviced in a circular way 2,3,4,5,0,1
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Transfer in terms of blocks of data
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Block contains frames
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For internal memories 4 clock cycles
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2 read + 2 write
DMA Operation Configuration
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Prior to transfer sub bank addressed registers have to be configured
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Which channel?
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Source and destination address
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Priorities and enabling of channels with DMPREC register 16 bit
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Size of the block DMA Sub bank Addressed RegistersName Address
Sub Addr
DescriptionDMSRC0 56h/57h 00h DMA channel 0 source address registerDMDST0 56h/57h 01h DMA channel 0 destination address registerDMCTR0 56h/57h 02h DMA channel 0 element count registerDMSFC0 56h/57h 03h DMA channel 0 sync select and frame count registerDMMCR0 56h/57h 04h DMA channel 0 transfer mode control registerDMSRC1………..DMSRCP 56h/57h 1Eh DMA source program page address (common channel)
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5 registers for each channel
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Total 30 registers for 6 channels
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+other control registers
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Total 62 registers
Register Sub addressing
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Technique used for configuring the DMA registers
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Intervention of CPU required
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Code for configuration is loaded into access registers DMSDI or DMSDN
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Sub address to be configured is loaded into DMSA
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DMSDI is auto-incremented
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DMSDI for entire sets of registers
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DMSDN for a single register access
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