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74F74

74F74

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datasheet of 74f74
datasheet of 74f74

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Published by: h_864794086 on May 19, 2013
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PhilipsSemiconductors
74F74
Dual D-type flip-flop
Product specificationSupercedes data of 1990 Oct 23IC15 Data Handbook1996 Mar 12
INTEGRATED CIRCUITS 
 
Philips SemiconductorsProduct specification
74F74Dual D-type flip-flop
21996 Mar 12853 0335 16554
FEATURE
Industrial temperature range available (–40
°
C to +85
°
C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuringindividual data, clock, set, and reset inputs; also true andcomplementary outputs. Set (SD) and reset (RD) are asynchronousactive low inputs and operate independently of the clock input. Whenset and reset are inactive (high), data at the D input is transferred tothe Q and Q outputs on the low-to-high transition of the clock. Datamust be stable just one setup time prior to the low-to-high transition ofthe clock for predictable operation. Clock triggering occurs at avoltage level and is not directly related to the transition time of thepositive-going pulse. Following the hold time interval, data at the Dinput may be changed without affecting the levels of the output.
PIN CONFIGURATION
1413121110987654321GNDV
CC
SD1Q1Q1CP1RD1D1RD0D0Q0CP0SD0Q0
SF00045 
TYPETYPICAL f
max
TYPICAL SUPPLY CURRENT (TOTAL)
74F74125MHz11.5mA
ORDERING INFORMATION
ORDER CODEDESCRIPTIONCOMMERCIAL RANGEV
CC
= 5V
±
10%,T
amb
= 0
°
C to +70
°
CINDUSTRIAL RANGEV
CC
= 5V
±
10%,T
amb
= –40
°
C to +85
°
CPKG. DWG. #
14-pin plastic DIPN74F74NI74F74NSOT27-114-pin plastic SON74F74DI74F74DSOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINSDESCRIPTION74F (U.L.) HIGH/LOWLOAD VALUE HIGH/LOW
D0, D1Data inputs1.0/1.020
µ
A/0.6mACP0, CP1Clock inputs (active rising edge)1.0/1.020
µ
A/0.6mASD0, SD1Set inputs (active low)1.0/3.020
µ
A/1.8mARD0, RD1Reset inputs (active low)1.0/3.020
µ
A/1.8mAQ0, Q1, Q0, Q1Data outputs50/331.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
µ
A in the high state and 0.6mA in the low state.
LOGIC SYMBOL
Q0Q0Q1Q15698V
CC
= Pin 14GND = Pin 7341111013CP0SD0RD0CP1SD1RD1D0D1212
SF00046 
IEC/IEEE SYMBOL
4321101112135698
&
SSC1C2R1D2DR
SF00047 
 
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 123
LOGIC DIAGRAM
V
CC
= Pin 14GND = Pin 75, 96, 8QQ4, 101, 133, 112, 12SDRDCPD
SF00048 
FUNCTION TABLE
INPUTSOUTPUTSOPERATINGSDRDCPDQQMODE
LHXXH LAsynchronous setHLXXLHAsynchronous resetLLXXHHUndetermined*HH
hHLLoad 1HH
lLHLoad 0HH
XNCNCHold
NOTES:
H=High voltage levelh=High voltage level one setup time prior to low-to-high clocktransitionL=Low voltage levell=Low voltage level one setup time prior to low-to-high clocktransitionNC=No change from the previous setupX=Dont care
=Low-to-high clock transition
=Not low-to-high clock transition*=This setup is unstable and will change when either set or resetreturn to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOLPARAMETERRATINGUNIT
V
CC
Supply voltage0.5 to +7.0VV
IN
Input voltage 0.5 to +7.0VI
IN
Input current30 to +5mAV
OUT
Voltage applied to output in high output state0.5 to V
CC
VI
OUT
Current applied to output in low output state40mAppCommercial range0 to +70
°
C
amb
 
 
uIndustrial range40 to +85
°
CT
stg
Storage temperature range65 to +150
°
C
RECOMMENDED OPERATING CONDITIONS
LIMITSMINNOMMAX
V
CC
Supply voltage4.55.05.5VV
IH
High-level input voltage2.0VV
IL
Low-level input voltage0.8VI
Ik
Input clamp current18mAI
OH
High-level output current1mAI
OL
Low-level output current20mAppCommercial range0+70
°
C
amb
 Industrial range40+85
°
C

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