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74-76_2

74-76_2

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Published by: Erman Al Hakim on May 20, 2013
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DM7476Dual Master-Slave J-K Flip-Flops with Clear, Preset, andComplementary Outputs
General Description
This device contains two independent positive pulse trig-gered J-K flip-flops with complementary outputs. The J andK data is processed by the flip-flop after a complete clockpulse. While the clock is low the slave is isolated from themaster. On the positive transition of the clock, the data fromthe J and K inputs is transferred to the master. While theclock is high the J and K inputs are disabled. On the negativetransition of the clock, the data from the master is transferredto the slave. The logic state of J and K inputs must not be al-lowed to change while the clock is high. The data is trans-fered to the outputs on the falling edge of the clock pulse. Alow logic level on the preset or clear inputs will set or resetthe outputs regardless of the logic levels of the other inputs.
Features
n
Alternate Military/Aerospace device (5476) is available.Contact a Fairchild Semiconductor SalesOffice/Distributor for specifications.
Connection Diagram Function Table
Inputs OutputsPR CLR CLK J K Q Q
L H X X X H LH L X X X L HL L X X X H(Note 1)H(Note 1)H H
I
L L Q
0
Q
0
H H
I
H L H LH H
I
L H L HH H
I
H H Toggle
H=High Logic LevelL=Low Logic LevelX=Either Low or High Logic Level
I
=Positive pulse data. The J and K inputs must be held constant while theclock is high. Data is transfered to the outputs on the falling edge of the clockpulse.Q
0
=The output logic level before the indicated input conditions were estab-lished.Toggle=Each output changes to the complement of its previous level oneach complete active high level clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when thepreset and/or clear inputs return to their inactive (high) level.
Dual-In-Line Package
DS006528-1
Order Number 5476DMQB, 5476FMQB,DM5476J, DM5476W or DM7476NSee Package Number J16A, N16E or W16A
March 1998
M7  4  7   6   u al   M a s t    er   S l    av e J  l   i     pl    o  p swi    t    C l    e ar    ,r   e s e t     , an d  C  om  pl    em en t    ar    y O u t     p u t    s
 © 1998 Fairchild Semiconductor Corporation DS006528
www.fairchildsemi.com
 
Absolute Maximum Ratings
(Note 2)Supply Voltage 7VInput Voltage 5.5VOperating Free Air Temperature RangeDM54 and 54 55˚C to +125˚CDM74 0˚C to +70˚CStorage Temperature Range −6C to +150˚C
Recommended Operating Conditions
Symbol Parameter DM5476 DM7476 UnitsMin Nom Max Min Nom Max
V
CC
Supply Voltage 4.5 5 5.5 4.75 5 5.25 VV
IH
High Level Input Voltage 2 2 VV
IL
Low Level Input Voltage 0.8 0.8 VI
OH
High Level Output Current 0.4 0.4 mAI
OL
Low Level Output Current 16 16 mAf
CLK
Clock Frequency (Note 8) 0 15 0 15 MHzt
W
Pulse Width Clock High 20 20(Note 8) Clock Low 47 47 nsPreset Low 25 25Clear Low 25 25t
SU
Input Setup Time (Notes 3, 8) 0
0
nst
H
Input Hold Time (Notes 3, 8) 0
0
nsT
A
Free Air Operating Temperature 55 125 0 70 ˚C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 4)V
I
Input Clamp Voltage V
CC
=Min, I
I
=12 mA 1.5 VV
OH
High Level Output V
CC
=Min, I
OH
=Max 2.4 3.4 VVoltage V
IL
=Max, V
IH
=MinV
OL
Low Level Output V
CC
=Min, I
OL
=Max 0.2 0.4 VVoltage V
IH
=Min, V
IL
=MaxI
I
Input Current
@
Max V
CC
=Max, V
I
=5.5V 1 mAInput VoltageI
IH
High Level Input V
CC
=Max J, K 40Current V
I
=2.4V Clock 80 µAClear 80Preset 80I
IL
Low Level Input V
CC
=Max J, K 1.6Current V
I
=0.4V Clock 3.2 mA(Note 7) Clear 3.2Preset 3.2I
OS
Short Circuit V
CC
=Max DM54 20 55 mAOutput Current (Note 5) DM74 18 55I
CC
Supply Current V
CC
=Max (Note 6) 18 34 mA
Note 3:
The symbol (
,
) indicates the edge of the clock pulse is used for reference (
) for rising edge, (
) for falling edge.
Note 4:
All typicals are at V
CC
=5V, T
A
=25˚C.
Note 5:
Not more than one output should be shorted at a time.
Note 6:
With all outputs open, I
CC
is measured with the Q and Q outputs high in turn. At the time of measurement the clock input is grounded.
Note 7:
Clear is measured with preset high and preset is measured with clear high.
www.fairchildsemi.com 2
 
Electrical Characteristics
(Continued)
Note 8:
T
A
=25˚C and V
CC
=5V.
Switching Characteristics
at V
CC
=5V and T
A
=25˚C
From (Input) R
L
=400
Symbol Parameter To (Output) C
L
=15 pF UnitsMin Max
f
MAX
Maximum Clock 15 MHzFrequencyt
PHL
Propagation Delay Time Preset 40 nsHigh to Low Level Output to Qt
PLH
Propagation Delay Time Preset 25 nsLow to High Level Output to Qt
PHL
Propagation Delay Time Clear 40 nsHigh to Low Level Output to Qt
PLH
Propagation Delay Time Clear 25 nsLow to High Level Output to Qt
PHL
Propagation Delay Time Clock to 40 nsHigh to Low Level Output Q or Qt
PLH
Propagation Delay Time Clock to 25 nsLow to High Level Output Q or Q
3 www.fairchildsemi.com

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