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A Compact Priority based Architecture Designed and Simulated for Data Sharing based on Reconfigurable Computing

A Compact Priority based Architecture Designed and Simulated for Data Sharing based on Reconfigurable Computing

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Journal of Computing (eISSN 2151-9617), 2013, call for papers, http://www.journalofcomputing.org/volume-5-issue-4-april-2013
Journal of Computing (eISSN 2151-9617), 2013, call for papers, http://www.journalofcomputing.org/volume-5-issue-4-april-2013

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Published by: Journal of Computing on May 27, 2013
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A Compact Priority based ArchitectureDesigned and Simulated for Data Sharingbased on Reconfigurable Computing
Bhavya Alankar and B K Kanaujia
 
Abstract
 
Reconfigurable Computing devices are coming very strongly in the digital hardware systems due to the availability of ready to use resources, parallel logic operations and reconfigurable designs. The usage of Reconfigurable systems in real time do-main is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. This paper mainly focuses on the application of Reconfigurable Computing systems in the data sharing domain and in order to depict thisapplication we have designed and simulated a priority based data sharing architecture through which we can interface two Proces-sors, which in turn can intercommunicate with each other. The main advantage of this architecture is that it is highly compact, easyto use and designed using a modular approach so that it could be easily implemented on Reconfigurable hardware. All the differentmodules along with the complete architecture is simulated using modelsim 6.0 and synthesized using Xilinx 7.1(iSE).
Index Terms
—Reconfigurable Computing, FPGA, Master-Slave processor.
——————————
 
 
——————————
1 I
NTRODUCTION
econfigurable computing based architectures offers aunique opportunity to address the memory accessand interfacing issues via customization. Improve-ments can be achieved by creating specialized architec-tures and
 
this architecture is mainly designed to explorethose opportunities of Reconfigurable computing [1], [2],[3]. In our design FPGA Spartan-3 kit [7] is acting as aninteractive device through which two processors can in-tercommunicate with each other such that one processorhas been given priority over the other processor and theirpriority is been decided by the conflict resolving block.Initially this design is simulated for 8-bit processor but itcan be extended up to any number of bits.The organization of this paper is as follows: Section 2shows the design overview and the details of differentfunctional modules. Section 3 depicts the simulationwaveform of the architecture. Section 4 discuss the con-clusion and future work
 
2 DESIGN
 
OVERVIEW
The
 
designed
 
architecture
 
is
 
fully
 
user
 
friendly,
 
flexible
 
and
 
synchronous.
 
One
 
Processor
 
acts
 
as
 
MASTER
 
and
 
the
 
other
 
Processor
 
acts
 
like
 
a
 
SLAVE
 
and
 
can
 
intercommuni
cate
 
with
 
each
 
other
 
[4].
 
Memory
 
provided
 
via
 
two
 
sepa
rate
 
and
 
fully
 
synchronous
 
ports.
 
Master
 
will
 
always
 
have
 
the
 
priority
 
over
 
slave
 
and
 
we
 
have
 
used
 
multiplexed
 
address
 
data
 
 bus
 
for
 
the
 
master
 
which
 
can
 
 be
 
used
 
for
 
slave
 
as
 
well.
 
Moreover
 
in
 
our
 
design
 
we
 
have
 
used
 
the
 
signals
 
of
 
peripheral
 
component
 
interconnect
 
 bus
 
[5]
 
for
 
the
 
master
 
processor
 
to
 
communicate
 
and
 
the
 
slave
 
processor
 
can
 
communicate
 
via
 
 busy,
 
address,
 
data
 
and
 
read
 
write
 
sig
nals
 
as
 
shown
 
in
 
Fig
 
1.,
 
 but
 
depending
 
upon
 
the
 
applica
tion
 
you
 
can
 
modify
 
them.
 
The
 
detailed
 
description
 
of
 
each
 
of
 
the
 
 blocks
 
depicted
 
in
 
the
 
main
 
 block
 
diagram
 
along
 
with
 
their
 
functional
 
description
 
and
 
device
 
utilization
 
summary
 
is
 
given
 
and
 
it
 
can
 
 be
 
seen
 
that
 
the
 
architecture
 
is
 
highly
 
compact
 
as
 
the
 
device
 
utilization
 
is
 
quiet
 
low.
 
2.1 Conflict Resolving Block
This
 
 block
 
grants
 
the
 
control
 
for
 
accessing
 
Dual
port
 
memory
 
to
 
the
 
requesting
 
system.
 
we
 
are
 
mainly
 
having
 
two
 
signals
 
viz
 
slave
 
request
 
(pr)
 
and
 
master
 
request
 
(pcirq)
 
and
 
the
 
main
 
functioning
 
of
 
this
 
 block
 
is
 
to
 
resolve
 
the
 
conflict
 
 between
 
them
 
 by
 
making
 
either
 
slave
 
 busy
 
(probussy)
 
or
 
master
 
 busy
 
(pci
 
 bussy)
 
as
 
low
 
(see
 
Table
 
1)
 
 TABLE
 
1 TRUTH
 
 TABLE
 
OF
 
CONFLICT
 
RESOLVING
 
BLOCK 
pcirqmasterprslave
 
pcibussymaster
 
Probussyslave
 
Low
 
Low
 
Low
 
High
 
Low
 
High
 
Low
 
High
 
High
 
Low
 
High
 
Low
 
High
 
High
 
High
 
High
 
 ———————————————— 
 
 
Bhavya Alankar is a Assistant Professor, Hamdard University, New Delhi,India.
 
B.K. Kanaujia is a Associate Profoessor, Ambedkar Institute of AdvancedCommunication Technologies & Research (AIACTR) Govt. of N.C.T..NewDelhi, India.
R
JOURNAL OF COMPUTING, VOLUME 5, ISSUE 4, APRIL 2013, ISSN (Online) 2151-9617https://sites.google.com/site/journalofcomputingWWW.JOURNALOFCOMPUTING.ORG33
 
 
Fig.1.
 
Compact
 
Architecture
 
of
 
Data
 
sharing
 
 between
 
Master
Slave.
 
Based on the information obtained from the abovetruth table, Two Boolean equations have been derivedand based on that equations, following digital design ofConflict resolving block has been obtained in Fig 2.Fig. 2.Digital design of conflict resolving block
The
 
device
 
utilization
 
summary
 
of
 
this
 
 block
 
imple
mented
 
on
 
the
 
Spartan
3
 
XC3S200
 
FPGA
 
(200
 
K
 
gates)
 
is
 
shown
 
in
 
Table
 
2.
 
And
 
It
 
shows
 
that
 
this
 
 block
 
was
 
de
signed
 
in
 
such
 
a
 
way
 
so
 
as
 
to
 
utilize
 
the
 
minimum
 
num
 ber
 
of
 
resources
 
on
 
FPGA.
 
 TABLE2DEVICE UTILIZATION SUMMARY OF CONFLICT RE-SOLVING BLOCK 
Number ofslices1 out of 1920
 
0%
 
Number of 4input LUTs
 
1 out of 3840
 
0%
 
Number ofbonded IOBs
 
3 out of 173
 
1%
 
2.2 Interactive Controller Blocks
When
 
 both
 
(Master
 
and
 
Slave)
 
request
 
for
 
the
 
access
 
of
 
memory
 
 ,The
 
Conflict
 
resolving
 
 block
 
drives
 
the
 
 busy
 
line
 
of
 
the
 
Master(pcibussy)
 
while
 
keeping
 
the
 
Slave
 
processor
 
in
 
a
 
wait
 
state
 
until
 
the
 
Master
 
finishes
 
its
 
operation.When
 
the
 
Master
 
generates
 
the
 
address
 
on
 
address
 
lines,
 
data
 
on
 
data
 
lines
 
and
 
write/read
 
signal
 
then
 
the
 
control
 
 block
 
check
 
for
 
the
 
 busy
 
line
 
of
 
Mas
ter.
 
When
 
the
 
control
 
 block
 
receives
 
the
 
 busy
 
line
 
of
 
Master
 
driven
 
to
 
low,
 
it
 
allows
 
the
 
address
 
on
 
valid
 
addresslines,data
 
on
 
valid
 
data
 
lines
 
and
 
wr_rd
 
signal
 
as
 
valid
 
wr_rd
 
signal
 
to
 
access
 
the
 
memory.
 
When
 
the
 
Slave
 
Processor
 
generates
 
the
 
address
 
on
 
address
 
lines,
 
data
 
on
 
data
 
lines
 
and
 
write/read
 
signal
 
then
 
the
 
con
trol
 
 block
 
check
 
for
 
the
 
 bussy
 
line
 
of
 
Slave
 
Processor.
 
When
 
the
 
control
 
 block
 
receives
 
the
 
 busy
 
line
 
of
 
Slave
 
Processor(probussy)
 
driven
 
to
 
low
 
it
 
allows
 
the
 
address
 
on
 
valid
 
address
 
lines,
 
data
 
on
 
val
 
id
 
data
 
lines
 
and
 
wr_rd
 
signal
 
as
 
valid
 
wr_rd
 
signal
 
to
 
access
 
the
 
memory
 
as
 
shown
 
in
 
Fig
 
3.
 
Fig.3.
 
Interactive
 
Controller
 
Block
 
Now
 
its
 
clear
 
that
 
the
 
main
 
function
 
of
 
the
 
Interactive
 
controller
 
 block
 
is
 
to
 
 just
 
select
 
or
 
decide
 
whether
 
the
 
Master
 
or
 
Slave
 
should
 
access
 
the
 
memory
 
on
 
the
 
 basis
 
of
 
the
 
output
 
of
 
Conflict
 
resolving
 
 block,
 
So
 
this
 
 block
 
is
 
 just
 
a
 
combination
 
of
 
the
 
Conflict
 
resolving
 
 block
 
and
 
the
 
memory
 
read
 
and
 
write
 
 block.
 
The
 
device
 
utilization
 
summary
 
of
 
the
 
Interactive
 
Con
troller
 
 block
 
implemented
 
on
 
the
 
Spartan
3
 
XC3S200
 
FPGA
 
(200
 
K
 
gates)
 
is
 
shown
 
in
 
Table
 
3.
 
As
 
this
 
 block
 
is
 
the
 
combination
 
of
 
mainly
 
the
 
muxes.
 
It
 
shows
 
the
 
num
 ber
 
of
 
slices
 
and
 
other
 
resources
 
available
 
utilized
 
in
 
im
plementing
 
the
 
design
 
on
 
FPGA.
 
JOURNAL OF COMPUTING, VOLUME 5, ISSUE 4, APRIL 2013, ISSN (Online) 2151-9617https://sites.google.com/site/journalofcomputingWWW.JOURNALOFCOMPUTING.ORG34
 
 
TABLE
 
3
 
DEVICE
 
UTILIZATION
 
SUMMARY
 
OF
 
INTERACTIVE
 
CONTROLLER
 
BLOCK
 
2.3 Memory block
It
 
is
 
one
 
of
 
the
 
main
 
 block
 
and
 
as
 
it
 
is
 
clear
 
from
 
the
 
name
 
that
 
the
 
main
 
purpose
 
of
 
this
 
 block
 
is
 
to
 
fulfill
 
the
 
storage
 
requirement
 
of
 
 both
 
the
 
Master
 
and
 
the
 
Slave
 
Processor.
 
This
 
storage
 
core
 
is
 
a
 
dual
 
port
 
memory
 
of
 
64
 
k
 
size,
 
fully
 
synchronous
 
such
 
that
 
the
 
data
 
is
 
to
 
 be
 
written
 
on
 
the
 
rising
 
edge
 
of
 
the
 
clock.
 
It
 
is
 
the
 
central
 
 block
 
which
 
de
pends
 
on
 
the
 
output
 
of
 
all
 
the
 
 blocks
 
such
 
that
 
first
 
of
 
all
 
the
 
Conflict
 
resolving
 
 block
 
will
 
decide
 
whether
 
Master
 
or
 
Slave
 
Processor
 
will
 
access
 
the
 
memory
 
and
 
depending
 
on
 
the
 
output
 
of
 
that
 
the
 
controller
 
 block
 
will
 
allow
 
the
 
valid
 
signals
 
to
 
access
 
the
 
memory
 
as
 
shown
 
in
 
Fig.4.
 
The
 
device
 
utilization
 
summary
 
of
 
the
 
memory
 
 block
 
implemented
 
on
 
the
 
Spartan
3
 
XC3S200
 
FPGA
 
(200
 
K
 
gates)
 
is
 
shown
 
in
 
Table
 
4.
 
It
 
shows
 
the
 
number
 
of
 
slices
 
and
 
other
 
resources
 
available
 
utilized
 
in
 
implementing
 
the
 
design
 
on
 
FPGA.
 
Fig. 4. Memory Block and Its Connectivity
TABLE
 
4
 
DEVICE
 
UTILIZATION
 
SUMMARY
 
OF
 
MEMORY
 
BLOCK
 
Number
 
of
 
slices
 
9
 
out
 
of
 
1920
 
0%
 
Number
 
of
 
slice
 
flip
 
flops
 
16
 
out
 
of
 
3840
 
0%
 
Number
 
of
 
4
 
input
 
LUTs
 
3
 
out
 
of
 
3840
 
0%
 
Number
 
of
 
 bonded
 
IOBs
 
49
 
out
 
of
 
173
 
28%
 
Number
 
of
 
BRAMs
 
1
 
out
 
of
 
12
 
8%
 
Number
 
of
 
GCLKs
 
2
 
out
 
of
 
8
 
25%
 
3. SIMULATION RESULTS
3.1
 
Master
 
Continuous
 
write
 
and
 
Slave
 
continuous
 
read
 
cycle:
 
In this the Master take the control from the Conflictresolving block by driving its bus request (pcirq) to accessthe memory. Then it broadcasts the address and data onaddress_data line such that first the address is send andby driving frame# as low and irdy# and trdy# drivinghigh the address is latched and then the data is send andby driving frame# high and driving irdy# and trdy# lowthe data is latched and in the mean time thepciwr(Master write) signal is also made low such that thedata is written in the memory.After the data is written into the memory the data can be continuously read by theSlave processor by just giving the address in the read ad-dress line and by applying read clock and in the meantime the pw(Slave write) signal should also be high andthe data ouput will be coming on the Slave processordata (pd) output line, Fig 5.Fig. 5. Master Write and Slave read cycle
Number
 
of
 
slices
 
1
 
out
 
of
 
1920
 
0%
 
Number
 
of
 
4
 
input
 
LUTs
 
1
 
out
 
of
 
3840
 
0%
 
Number
 
of
 
 bonded
 
IOBs
 
4
 
out
 
of
 
173
 
1%
 
Number
 
of
 
GCLKs
 
1out
 
of
 
8
 
15%
 
JOURNAL OF COMPUTING, VOLUME 5, ISSUE 4, APRIL 2013, ISSN (Online) 2151-9617https://sites.google.com/site/journalofcomputingWWW.JOURNALOFCOMPUTING.ORG35

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