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usb implementation using utmi macrocell

usb implementation using utmi macrocell

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Published by rockfloyd
NOTE: it usually takes some time to reply to your queries because i have a lot of work and i'm not on scribd frequently so please be patient. thanks

The project deals with VHDL implementation of Universal Transceiver Macrocell Interface of USB 2.0 and testing the same by downloading it into FPGA (Spartan2).

The Universal Serial Bus (USB) Transceiver Macrocell Interface (UTMI) is a two wire, bi-directional serial bus interface. The USB 2.0 specifications define three types of UTMI implementations depends on data transmission rates, those are Low Speed(1.5MHz) only (LS), Full Speed (12MHz) only (FS) and High Speed (480MHz)/Full speed (12MHz) (HS).
UTMI consists of transmission and receiving sections, In which the transmitter of the UTMI sends data to different USB device through D+ and D- lines where as the receiver gets data on the same lines. This presentation reveals the FPGA implementation of UTMI with HS/FS transmission rate providing with USB 2.0 specifications. Further UTMI has been designed by using VHDL code and simulated, synthesized and targeted to the Spartan2 family of FPGA in the Xilinx environment.

Implementation strategy for UTMI:

The VHDL code for each block is written in synthesizable way. Test benches are written for each module and are simulated in Model Sim environment. After satisfactory functioning of each block, these blocks are combined to form the transceiver. This transceiver block is then tested by generating appropriate test vectors through test bench. After verification of the transceiver module, it is dumped into the FPGA (Spartan 2) and it is verified.
NOTE: it usually takes some time to reply to your queries because i have a lot of work and i'm not on scribd frequently so please be patient. thanks

The project deals with VHDL implementation of Universal Transceiver Macrocell Interface of USB 2.0 and testing the same by downloading it into FPGA (Spartan2).

The Universal Serial Bus (USB) Transceiver Macrocell Interface (UTMI) is a two wire, bi-directional serial bus interface. The USB 2.0 specifications define three types of UTMI implementations depends on data transmission rates, those are Low Speed(1.5MHz) only (LS), Full Speed (12MHz) only (FS) and High Speed (480MHz)/Full speed (12MHz) (HS).
UTMI consists of transmission and receiving sections, In which the transmitter of the UTMI sends data to different USB device through D+ and D- lines where as the receiver gets data on the same lines. This presentation reveals the FPGA implementation of UTMI with HS/FS transmission rate providing with USB 2.0 specifications. Further UTMI has been designed by using VHDL code and simulated, synthesized and targeted to the Spartan2 family of FPGA in the Xilinx environment.

Implementation strategy for UTMI:

The VHDL code for each block is written in synthesizable way. Test benches are written for each module and are simulated in Model Sim environment. After satisfactory functioning of each block, these blocks are combined to form the transceiver. This transceiver block is then tested by generating appropriate test vectors through test bench. After verification of the transceiver module, it is dumped into the FPGA (Spartan 2) and it is verified.

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Published by: rockfloyd on May 05, 2009
Copyright:Attribution Non-commercial

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03/13/2013

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FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATIONS
1. INTRODUCTION
As operating frequencies go up it becomes more difficult to compileVHDL code without modification. This document defines an interface towhich ASIC and peripheral vendors can develop.The figure1 shows the block diagram of USB controller, which is present in every USB device. There are three major functional blocks in aUSB 2.0controller. the USB 2.0 Transceiver Macrocell Interface (UTMI),the Serial Interface Engine (SIE), and the device specific logic.
 
Figure1: Block diagram of USB controller.
UTMI
This block handles the low level USB protocol and signaling. Thisincludes features such as; data serialization and deserialization, bit stuffing
SAI SPURTHI INSTITUE OF TECHNOLOGYPage
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FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATIONS
and clock recovery and synchronization. The primary focus of this block isto shift the clock domain of the data from the USB 2.0 rate to one that iscompatible with the general logic in the ASIC.The UTMI is designed to support HS/FS, FS Only and LS Only UTMimplementations. The three options allow a single SIE implementation to beused with any speed USB transceiver. A vendor can choose the transceiver  performance that best meets their needs.A HS/FS implementation of the transceiver can operate at either a 480Mb/s or a 12 Mb/s rate. Two modes of operation are required to properlyemulate High-speed device connection and suspend/resume features of USB2.0, as well as Full-speed connections if implementing a Dual-Mode device.FS Only and LS Only UTM implementations do not require the speedselection signals since there is no alternate speed to switch to.
Serial Interface Engine
This block can be further sub-divided into 2 types of sub-blocks; theSIE Control Logic and the Endpoint logic. The SIE Control Logic containsthe USB PID and address recognition logic, and other sequencing and statemachine logic to handle USB packets and transactions. The Endpoint Logiccontains the endpoint specific logic: endpoint number recognition, FIFOsand FIFO control, etc. Generally the SIE Control Logic is required for anyUSB implementation while the number and types of endpoints will vary asfunction of application and performance requirements.SIE logic module can be developed by peripheral vendors or  purchased from IP vendors. The standardization of the UTMI allowscompatible SIE VHDL to drop into an ASIC that provides the macro cell.
Device Specific Logic:
SAI SPURTHI INSTITUE OF TECHNOLOGYPage
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FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATIONS
This is the glue that ties the USB interface to the specific application of thedevice.
2. USB TRANCIEVER MACROCELL INTERFACE(UTMI)
2.1 Introduction to UTMI
Universal Serial Bus(USB) Transceiver Macrocell Interface (UTMI)is one of the most important blocks of USB Controller. This block handlesthe low level USB protocol and signaling. This includes features such asdata serialization, de serialization, bit stuffing, bit de stuffing, Non Return toZero Invert on ‘1’(NRZI) encoding, decoding, clock recovery andsynchronization. The primary focus of this block is to shift the clock domainof the data from the USB 2.0 rate to one that this compatible with thegeneral logic in the ASIC.
Key features of the USB 2.0 Transceiver
Supports 480 Mbit/s "High Speed" (HS)/ 12 Mbit/s “Full Speed” (FS),FS Only and "Low Speed" (LS) Only 1.5 Mbit/s serial datatransmission rates.
Utilizes 8-bit parallel interface to transmit and receive USB 2.0 cabledata
SYNC/EOP generation and checking
High Speed and Full Speed operation to support the development of "Dual Mode" devices
Data and clock recovery from serial stream on the USB
Bit-stuffing/unstuffing; bit stuff error detection
SAI SPURTHI INSTITUE OF TECHNOLOGYPage
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