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LOGIC CIRCUITS
•
COMBINATIONAL LOGIC CIRCUIT
•
SEQUENTONAL LOGIC CIRCUIT
DESIGN PROCEDURE
•THE PROBLEM IS STATED•INPUT |& OUTPUT VARIABLES ARE DETERMINED•INPUT & OUTPUT VARIABLES ARE ASSIGNEDLETTER SYMBOLS•TRUTH TABLE IS DERIVED TO DEFINE THERELATIONSHIPS B/W INPUTS & OUTPUTS•THE SIMPLIFIED BOOLEAN FUNCTION FOR EACHOUTPUT IS OBTAINED•THE LOGIC DIAGRAM IS DRAWN
CONSTRAINTS FOR A PRACITAL DESIGN
•MINIMUM NUMBER OF GATES•MINIMUM NUMBER OF INPUTS TO A GATE•MINIMUM PROPAGATION TIME OF THESIGNAL THROUGH THE CIRCUIT•MINIMUM NUMBER OF INTERCONNECTIONS•LIMITATIONS OF THE DRIVINGCAPABILITIES OF EACH GATE
COMBINATIONAL LOGIC
CIRCUIT
n INPUTVARIABLESm OUTPUTVARIABLES
BLOCK DIAGRAM OF A COMBINATIONAL CIRCUIT
ADDERS
HALF ADDERS
0111
1001
1010
0000
SCyx
S = x’ y + x y’
C = xy
of 00
Digital And Logic Design No. 3 (Logic Circuits) from APCOMS
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| Upload Date: | 05/05/2009 |
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