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74LVC1G08

74LVC1G08

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Published by nevdull
74LVC1G08
74LVC1G08

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Published by: nevdull on Jul 04, 2013
Copyright:Attribution Non-commercial

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07/04/2013

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1.General description
The 74LVC1G08 provides one 2-input AND function.Inputscanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallowstheuseofthesedevices as translators in mixed 3.3V and5V applications.Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and falltime.This device is fully specified for partial power-down applications using I
OFF
.TheI
OFF
circuitry disables the output, preventing the damaging backflow current throughthe device when it is powered down.
2.Features
s
Wide supply voltage range from 1.65Vto5.5V
s
High noise immunity
s
Complies with JEDEC standard:
x
JESD8-7 (1.65Vto1.95V)
x
JESD8-5 (2.3Vto2.7V)
x
JESD8-B/JESD36 (2.7Vto3.6V)
s
±
24mA output drive (V
CC
=3.0V)
s
CMOS low power consumption
s
Latch-up performance
250mA
s
Direct interface with TTL levels
s
Inputs accept voltages up to 5V
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000V
x
MM JESD22-A115-A exceeds 200V
s
Multiple package options
s
Specified from
40
°
C to+85
°
C and
40
°
C to+125
°
C
74LVC1G08
Single 2-input AND gate
Rev. 07 17 July 2007Product data sheet
 
74LVC1G08_7© NXP B.V. 2007. All rights reserved.
Product data sheetRev. 07 17 July 20072 of 14
NXP Semiconductors
74LVC1G08
Single 2-input AND gate
3.Ordering information4.Marking5.Functional diagram
Table 1.Ordering informationType numberPackageTemperaturerangeNameDescriptionVersion
74LVC1G08GW
40
°
Cto+125
°
CTSSOP5plastic thin shrink small outline package; 5 leads;body width 1.25 mmSOT353-174LVC1G08GV
40
°
Cto+125
°
CSC-74Aplastic surface-mounted package; 5 leadsSOT75374LVC1G08GM
40
°
Cto+125
°
CXSON6plastic extremely thin small outline package;noleads; 6 terminals; body1
×
1.45
×
0.5mmSOT88674LVC1G08GF
40
°
C to +125
°
CXSON6plastic extremely thin small outline package;noleads; 6 terminals; body 1
×
1
×
0.5mmSOT891
Table 2.MarkingType numberMarking code
74LVC1G08GWVE74LVC1G08GVV0874LVC1G08GMVE74LVC1G08GFVE
Fig 1.Logic symbolFig 2.IEC logic symbolFig 3.Logic diagram
mna113 
BAY214
mna114 
24&1
mna221
ABY
 
74LVC1G08_7© NXP B.V. 2007. All rights reserved.
Product data sheetRev. 07 17 July 20073 of 14
NXP Semiconductors
74LVC1G08
Single 2-input AND gate
6.Pinning information
6.1Pinning6.2Pin description
7.Functional description
[1]H=HIGH voltage level; L=LOW voltage level
Fig 4.Pin configuration SOT353-1and SOT753Fig 5.Pin conguration SOT886Fig 6.Pin conguration SOT891
74LVC1G08
B V
CC
AGND Y
001aab638 
12354
74LVC1G08
A
001aab639 
BGNDn.c.V
CC
YTransparent top view231546
74LVC1G08
A
001aae978 
BGNDn.c.V
CC
YTransparent top view231546
Table 3.Pin descriptionSymbolPinDescriptionSOT353-1/SOT753SOT886/SOT891
B11data inputA22data inputGND33ground (0V)Y44data outputn.c.-5not connectedV
CC
56supply voltage
Table 4.Function table
InputOutputABY
LLLLHLHLLHHH

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